Micron Technology, Inc. patent applications published on December 7th, 2023

Summary of the patent applications from Micron Technology, Inc. on December 7th, 2023

Micron Technology, Inc. has recently filed several patents related to memory architecture and memory devices. These patents aim to improve the performance, efficiency, and reliability of memory devices by reducing capacitance, increasing memory capacity, and enhancing data storage and retrieval capabilities.

Some notable applications of these patents include:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage systems in servers and data centers.
• Embedded memory in integrated circuits for various applications.

Summary of recent patents filed by Micron Technology, Inc.:

1. Patent: Ferroelectric Memory Architecture with Gap Region

  * Describes a memory architecture with a gap region between memory cells to reduce capacitance and eliminate undesirable coupling during memory operations.
  * The gap region contains a fluid with a low dielectric constant to further reduce capacitance and improve memory device speed and resource consumption.

2. Patent: Integrated Assemblies and Memory Devices

  * Describes integrated assemblies and memory devices with specific components and arrangements, including leaker devices and conductive contact regions.
  * These structures improve the performance and reliability of memory devices and can be used in various electronic systems.

3. Patent: Memory Device with Transistor and Capacitor

  * Describes a memory device with an array of memory cells, each consisting of a transistor and a capacitor.
  * The memory cell design includes specific arrangements of electrodes, insulators, and conductive contact regions to enhance functionality and increase memory capacity.

4. Patent: Memory Cells with Conductive Pillars and Dielectric Barriers

  * Describes memory cells with conductive pillars and low permittivity dielectric barriers to improve performance and reliability.
  * The manufacturing process involves depositing and removing dielectric material to create the desired barriers between memory cells.

5. Patent: Microelectronic Device with Stack Structure and Memory Pillar

  * Describes a microelectronic device with a stack structure, memory pillar, and boron-containing material.
  * The device design enhances memory capacity, data storage, and overall performance of microelectronic devices.

6. Patent: Method of Forming Microelectronic Device

  * Describes a method for forming a microelectronic device with conductive interconnect structures and additional isolation material.
  * The method improves conductivity, isolation, and overall efficiency of the device manufacturing process.

7. Patent: Merged Cavities and Buried Etch Stops for Memory Arrays

  * Describes a method for forming memory arrays with merged cavities and etch stops.
  * The technology improves memory array performance, manufacturing efficiency, and reliability.

Notable Applications:

• Memory devices for electronic devices, data storage systems, and integrated circuits.
• Improved data storage and retrieval capabilities.
• Increased memory capacity and speed.
• Enhanced performance, reliability, and durability of electronic devices.
• Reduced power consumption and improved energy efficiency.

Patent applications for Micron Technology, Inc. on December 7th, 2023

PERFORMING SECURITY FUNCTIONS USING DEVICES HAVING EMBEDDED HARDWARE SECURITY MODULES (17858568)

Main Inventor

Sourin SARKAR

GERMANIUM PRECURSORS, METHODS OF FORMING THE GERMANIUM PRECURSORS, AND PRECURSOR COMPOSITIONS COMPRISING THE GERMANIUM PRECURSORS (18327840)

Main Inventor

Gurtej S. Sandhu

VEHICLE COMMUNICATION AND NAVIGATION SYSTEMS FOR ROAD SAFETY (17859045)

Main Inventor

Aysha Shanta

AUTOMATED RENDERING OF DATA FLOW ARCHITECTURE FOR NETWORKED COMPUTER SYSTEMS (17830780)

Main Inventor

Jonathan Blaine Nielsen

VOLTAGE FREQUENCY SCALING BASED ON ERROR RATE (17893850)

Main Inventor

Leon Zlotnik

APPARATUSES AND METHODS FOR PROVIDING INTERNAL POWER VOLTAGES (17893946)

Main Inventor

Ki-Jun Nam

MANAGING QUAD-LEVEL CELL COMPACTION STRATEGY OF A MEMORY DEVICE (17830166)

Main Inventor

Vamsi Pavan Rayaprolu

BIT ERROR MANAGEMENT IN MEMORY DEVICES (18049121)

Main Inventor

Jeremy BINFET

PREDICTIVE DATA PRE-FETCHING IN A DATA STORAGE DEVICE (18454743)

Main Inventor

Alex Frolikov

Brief explanation

The patent application describes a data storage system that includes non-volatile media, a buffer memory, a processing device, and a data pre-fetcher. The data pre-fetcher receives commands to be executed in the data storage system and uses a predictive model to identify commands for pre-fetching. 

• The data pre-fetcher retrieves a portion of data from the non-volatile memory before the command is executed and stores it in the buffer memory.
• This retrieval and storage process can be done concurrently with the execution of multiple commands, reducing the impact of latency on other commands being executed at the same time.

Potential Applications

• This technology can be applied in various data storage systems, such as hard drives, solid-state drives, and cloud storage platforms.
• It can improve the performance and efficiency of data storage systems by reducing latency and optimizing data retrieval.

Problems Solved

• Latency is a common issue in data storage systems, causing delays in executing commands and impacting overall system performance.
• By pre-fetching data before executing commands, this technology helps to minimize the latency impact and improve the efficiency of data storage systems.

Benefits

• Improved performance: By pre-fetching data, the system can execute commands more quickly, reducing overall latency and improving system performance.
• Enhanced efficiency: The concurrent retrieval and storage of data allow for better utilization of system resources and optimize the execution of multiple commands simultaneously.
• Reduced latency impact: By pre-fetching data, the latency impact on other commands being executed concurrently is minimized, leading to smoother and more efficient operation of the data storage system.

Abstract

A data storage system having non-volatile media, a buffer memory, a processing device, and a data pre-fetcher. The data pre-fetcher receives commands to be executed in the data storage system, provides the commands as input to a predictive model, obtains at least one command identified for pre-fetching, as output from the predictive model having the commands as input. Prior to the command being executed in the data storage device, the data pre-fetcher retrieves, from the non-volatile memory, at least a portion of data to be used in execution of the command; and stores the portion of data in the buffer memory. The retrieving and storing the portion of the data can be performed concurrently with the execution of many commands before the execution of the command, to reduce the latency impact of the command on other commands that are executed concurrently with the execution of the command.

ACCESS HEATMAP IMPLEMENTATIONS AT A HOST DEVICE (17831242)

Main Inventor

Nabeel Meeramohideen Mohamed

Brief explanation

The abstract describes methods, systems, and devices for implementing access heatmaps at a host device. These heatmaps help track access operations performed at a memory device. Here are the key points:

• The host device uses access operation monitoring performed at a memory device.
• The memory device maintains a storage location to track access operation occurrence.
• Access operations of a specific address can be mapped to multiple fields.
• Each field is associated with access operations of a subset of addresses.
• The memory device can be configured or accessed based on indications from the host device.
• This allows for dynamic access operation monitoring based on different operating conditions.
• The host device can evaluate minimum values associated with addresses to determine data distribution across memory.

Potential Applications

• Memory management in computer systems
• Performance optimization in data storage devices
• Data analysis and visualization tools

Problems Solved

• Lack of efficient monitoring and tracking of access operations in memory devices
• Difficulty in determining data distribution across memory
• Inability to dynamically adjust access operation monitoring based on operating conditions

Benefits

• Improved memory management and performance optimization
• Real-time monitoring and tracking of access operations
• Dynamic adjustment of access operation monitoring based on operating conditions

Abstract

Methods, systems, and devices for access heatmap implementations at a host device are described. A host device may leverage access operation monitoring that is performed at a memory device, including various examples of signaling and management of monitoring configurations. For example, a memory device may maintain a storage location for tracking access operation occurrence, for which access operations of a given address may be mapped to multiple fields, and for which each field may be associated with access operations of a respective subset of the addresses. In some examples, such registers may be configured or accessed based on indications (e.g., commands, requests) from a host device, which may support dynamic access operation monitoring that is responsive to various operating conditions. In some examples, the host device may perform evaluations based on such minimum values associated with respective addresses to determine a distribution of data across various portions of memory.

DIE FAMILY MANAGEMENT ON A MEMORY DEVICE USING BLOCK FAMILY ERROR AVOIDANCE (17856771)

Main Inventor

Steven Michael Kientz

Brief explanation

The patent application describes a method for identifying a target block family in a memory device based on periodic program erase cycles (PECs). The target block family consists of multiple blocks.

• The target block family is identified periodically every predetermined number of program erase cycles (PECs).
• Each block family includes multiple blocks.
• The method involves obtaining the temporal voltage shift of each block in a subset of blocks from each die associated with the target block family.
• A die measurement is calculated for each die based on the average temporal voltage shifts of the subset of blocks.
• Each die is assigned to a die family based on its die measurement.

Potential Applications

• Memory device management and optimization.
• Improving the efficiency and performance of memory devices.

Problems Solved

• Efficient identification and management of block families in memory devices.
• Optimization of memory device performance.

Benefits

• Improved memory device performance.
• Enhanced memory device management and optimization.

Abstract

A target block family of a plurality of block families is identified periodically every predetermined number of program erase cycles (PECs) of a memory device. Each block family includes a plurality of blocks. A respective temporal voltage shift of each block of a subset of blocks of the target block family from each die of a plurality of dies associated with the target block family is obtained. A respective die measurement for each respective die is obtained based on an average of the respective temporal voltage shifts of the subset of blocks from each die. Each respective die to a respective die family of a plurality of consecutive die families is assigned based on the respective die measurement for each respective die.

CONTROLLER FOR A MEMORY DEVICE AND A STORAGE DEVICE (18199422)

Main Inventor

Venkata Kiran Kumar Matturi

Brief explanation

The abstract describes a controller that is connected to a storage device and a memory device, but not directly to a host. The controller monitors multiple regions of the memory device to check if they are full, and if so, it reads the data from those regions. After reading the data, the controller stores it in the storage device and deletes it from the memory regions. It then informs the host that the data has been moved from the memory device to the storage device. The controller can operate independently from the host.

• The controller is directly connected to a storage device and a memory device, but not to a host.
• It monitors multiple regions of the memory device to determine if they are full.
• If the regions are full, the controller reads the data from those regions.
• After reading the data, the controller stores it in the storage device.
• The data is then deleted from the memory regions.
• The controller informs the host that the data has been moved from the memory device to the storage device.
• The controller can function independently from the host.

Potential Applications

• Data storage systems
• Memory management systems
• Embedded systems

Problems Solved

• Efficient data storage and management
• Optimal utilization of memory regions
• Seamless data transfer from memory to storage

Benefits

• Improved performance and efficiency
• Reduced memory usage
• Simplified data management
• Independent operation from the host

Abstract

A controller can be directly coupled to a storage device and a memory device but not a host. The controller can monitor a plurality of regions of the memory device to determine whether the plurality of regions meet a criterion for fullness and responsive to determining that the plurality of regions meet the criterion, read data from the plurality of regions. The controller can, responsive to reading the data from the plurality of regions, store the data in the storage device and delete the data from the plurality of regions. The controller can further, responsive to storing the data, report to a host that the data has been moved from the memory device to the storage device. The controller can be implemented independent from the host.

MEMORY SYSTEM REFRESH MANAGEMENT (17965957)

Main Inventor

Yang Lu

Brief explanation

The abstract describes a patent application related to memory system refresh management. It explains that a refresh operation can be performed on a set of memory cells in a memory device. The operation involves receiving a mode register write command and writing mode register data associated with the command. The refresh operation is then performed on the set of memory cells at the address location indicated by the written mode register data.

• A refresh operation is performed on a set of memory cells in a memory device.
• The memory device has multiple sets of memory cells corresponding to different portions of the memory array.
• The refresh operation involves receiving a mode register write command.
• Mode register data associated with the command is written.
• The refresh operation is performed on the set of memory cells at the address location indicated by the written mode register data.

Potential Applications

• Memory system management in various electronic devices.
• Improving the performance and reliability of memory systems in computers, smartphones, and other devices.

Problems Solved

• Ensuring the proper functioning and longevity of memory cells in a memory device.
• Managing the refresh operation efficiently to avoid data loss or corruption.

Benefits

• Enhanced performance and reliability of memory systems.
• Improved data integrity and longevity of memory cells.
• Efficient management of refresh operations in memory devices.

Abstract

Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.

APPARATUS WITH RESPONSE COMPLETION PACING (18049973)

Main Inventor

Ying Huang

Brief explanation

The patent application describes methods, apparatuses, and systems for controlling latency in response completion pacing. It introduces an apparatus that uses response completion pacing to regulate the timing of output communications to the host. This is achieved by utilizing a ready response queue in the memory device to temporarily store retrieved data. The apparatus includes logic that is connected to the ready response queue and is configured to send the data in the queue based on a cadence period. The logic can also dynamically adjust the storage capacity of the ready response queue and/or the cadence period.

• The patent application introduces an apparatus that utilizes response completion pacing to control the timing of output communications to the host.
• The apparatus includes a ready response queue in the memory device to temporarily store retrieved data.
• Logic connected to the ready response queue is responsible for sending the data in the queue according to a cadence period.
• The logic can dynamically adjust the storage capacity of the ready response queue and/or the cadence period.

Potential Applications

This technology can have various applications in the field of memory devices and data communication. Some potential applications include:

• Improving the performance and efficiency of memory devices in computer systems.
• Enhancing the speed and responsiveness of data transfers between storage devices and hosts.
• Optimizing the latency control in cloud computing environments.
• Streamlining data communication processes in high-speed networks.

Problems Solved

The technology presented in the patent application addresses several problems related to latency control and data communication. These problems include:

• Inefficient timing of output communications, leading to delays and reduced performance.
• Lack of flexibility in adjusting the storage capacity of response queues, resulting in suboptimal resource utilization.
• Difficulty in dynamically adapting the cadence period to match changing communication requirements.
• Inadequate control over latency in memory devices, leading to slower data transfers and decreased system efficiency.

Benefits

The described technology offers several benefits and advantages, including:

• Improved timing control of output communications, resulting in reduced latency and faster data transfers.
• Enhanced flexibility in adjusting the storage capacity of response queues, leading to better resource management.
• Dynamic adaptation of the cadence period to match changing communication requirements, optimizing system performance.
• Efficient latency control in memory devices, improving overall system efficiency and responsiveness.

Abstract

Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

VOLTAGE WINDOW ADJUSTMENT (17887244)

Main Inventor

Zhenming Zhou

Brief explanation

The patent application describes a system that includes a memory component and a processing device. The memory component consists of a group of memory cells, while the processing device is connected to the memory component.

• The processing device is programmed to use a specific voltage window for a set of memory cells during a certain time period.
• If the processing device detects that the error rate of a subset of the memory cells exceeds a predefined threshold, it will take action.
• In response to the high error rate, the processing device will switch to a different voltage window for the entire set of memory cells during a different time period.

Potential applications of this technology:

• This technology can be used in computer systems, particularly in memory components, to improve error detection and correction.
• It can be applied in various industries that rely on reliable and accurate data storage, such as telecommunications, data centers, and cloud computing.

Problems solved by this technology:

• Memory cells can sometimes experience errors, which can lead to data corruption or loss.
• By monitoring the error rate and adjusting the voltage window accordingly, this technology helps to identify and mitigate errors in memory cells.

Benefits of this technology:

• Improved reliability and accuracy of data storage.
• Enhanced error detection and correction capabilities.
• Increased overall system performance and efficiency.

Abstract

An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.

WEAR LEVELING IN SOLID STATE DRIVES (18452020)

Main Inventor

Zoltan Szubbocsev

Brief explanation

The patent application describes a computer storage device that includes a host interface, a controller, non-volatile storage media with different types of memory units, and firmware. The firmware guides the controller to perform two main tasks: 

• Generate an address map that links logical addresses to physical addresses of the memory units with different types.
• Adjust the address map based on the program erase budgets to distribute wear evenly across the memory units of different types.

Potential applications of this technology include:

• Solid-state drives (SSDs) used in computers, laptops, and servers.
• Flash memory devices used in smartphones, tablets, and other portable devices.
• Embedded storage systems in automotive, aerospace, and industrial applications.

The problems solved by this technology are:

• Uneven wear and degradation of memory units with different types, which can lead to premature failure and reduced lifespan of the storage device.
• Inefficient utilization of the storage media due to uneven wear, resulting in reduced overall storage capacity and performance.

The benefits of this technology are:

• Extended lifespan and improved reliability of the storage device by evenly distributing wear across memory units.
• Optimal utilization of the storage media, maximizing storage capacity and performance.
• Enhanced user experience with faster access times and improved data integrity.

Abstract

A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.

FIFO MEMORY ERROR CONDITION DETECTION (17831344)

Main Inventor

Lance P. Johnson

Brief explanation

The abstract describes an apparatus that includes circuitry and a FIFO memory. The circuitry includes a write pointer that operates at a certain rate, while a read pointer operates at a different rate. The apparatus also includes third circuitry that detects errors in the FIFO memory based on the positions of the write and read pointers.

• The apparatus includes circuitry for managing a FIFO memory.
• The write pointer of the FIFO memory operates at a specific rate.
• The read pointer of the FIFO memory operates at a different rate.
• The apparatus includes third circuitry that detects errors in the FIFO memory.
• The error detection is based on the positions of the write and read pointers.

Potential Applications

• Data storage and retrieval systems
• Communication systems
• Real-time data processing systems

Problems Solved

• Ensures accurate and reliable data transfer between different circuitry components.
• Detects and alerts for errors in the FIFO memory.

Benefits

• Improves data integrity and reliability.
• Facilitates efficient data transfer between different components.
• Enables real-time error detection and troubleshooting.

Abstract

An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.

MANAGING ERROR COMPENSATION USING CHARGE COUPLING AND LATERAL MIGRATION SENSITIVITY (17860701)

Main Inventor

Mustafa N. Kaynak

Brief explanation

The abstract of this patent application describes a method for determining the dependence of memory cells on adjacent cells in a memory device. The method involves calculating a metric for each memory cell that reflects its sensitivity to changes in the threshold voltage of neighboring cells. Based on these metrics, an aggregate measure of adjacent cell dependence is determined for each wordline. This measure is then compared to a threshold value to identify wordline groups with high and low adjacent cell dependence. A record is created to store the location of wordlines with low dependence on adjacent cells.

• The patent application describes a method for analyzing the sensitivity of memory cells to changes in the threshold voltage of neighboring cells.
• The method calculates a metric for each memory cell to determine its sensitivity to adjacent cell threshold voltage changes.
• An aggregate measure of adjacent cell dependence is determined for each wordline based on the calculated metrics.
• The aggregate measure is compared to a threshold value to identify wordline groups with high and low adjacent cell dependence.
• A record is created to store the location of wordlines with low dependence on adjacent cells.

Potential Applications

This technology can be applied in various areas where memory devices are used, such as:

• Semiconductor manufacturing: The method can be used to optimize the design and production of memory devices, leading to improved performance and reliability.
• Data storage: By identifying wordlines with low adjacent cell dependence, the method can help in designing more robust and efficient memory systems.
• Computer hardware: The technology can be integrated into computer systems to enhance memory management and improve overall system performance.

Problems Solved

The technology addresses the following problems:

• Memory cell sensitivity: By determining the sensitivity of memory cells to changes in adjacent cell threshold voltages, the method helps identify potential issues that can affect memory performance and reliability.
• Wordline optimization: By identifying wordlines with low adjacent cell dependence, the method allows for the optimization of memory systems, reducing the impact of neighboring cells on memory operations.
• Manufacturing efficiency: The method enables more efficient manufacturing processes by providing insights into the dependence of memory cells on adjacent cells, allowing for targeted improvements and optimizations.

Benefits

The technology offers the following benefits:

• Improved memory performance: By optimizing wordline groups based on adjacent cell dependence, memory systems can operate more efficiently and reliably.
• Enhanced memory reliability: Identifying and addressing potential issues related to adjacent cell dependence can improve the overall reliability and lifespan of memory devices.
• Manufacturing cost savings: By providing insights into memory cell dependence, the method enables targeted improvements in manufacturing processes, reducing costs and improving yield.

Abstract

Embodiments disclosed can include determining, for each memory cell connected to each wordline, a respective value of a metric that reflects a sensitivity of a threshold voltage associated with the memory cell to a change in a threshold voltage of an adjacent cell and determining, for each wordline, based on the determined sensitivity for each memory cell, a respective aggregate measure of adjacent cell dependence. They can further include comparing the determined aggregate measure of adjacent cell dependence to a threshold dependence value. They can also include identifying a first wordline group having wordlines with high adjacent cell dependence and a second wordline group having wordlines with low adjacent cell dependence and storing a record referencing the wordlines of the second wordline group, the record indicating a corresponding location on the die of the memory device.

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM (17863000)

Main Inventor

Kishore Kumar Muchherla

Brief explanation

The patent application describes a system that includes a memory device and a processing device. The processing device receives read commands for a set of memory cells and increments a read counter based on the time difference between the commands. When the read counter reaches a certain threshold, a data integrity scan is performed on the memory cells.

• Memory device with multiple memory cells
• Processing device receives read commands for a set of memory cells
• Read counter is incremented based on the time difference between commands
• Data integrity scan is performed when the read counter reaches a threshold

Potential Applications

• Data storage systems
• Computer memory devices
• Solid-state drives

Problems Solved

• Ensures data integrity in memory cells
• Detects potential errors or corruption in memory cells

Benefits

• Improved reliability of memory devices
• Early detection of data corruption
• Prevents data loss or errors in memory cells

Abstract

A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

STORING NON-VOLATILE MEMORY INITIALIZATION FAILURES (17889810)

Main Inventor

Qi Dong

Brief explanation

The present disclosure relates to a method for storing non-volatile memory initialization failures. Here is a simplified explanation of the abstract:

• The method involves initializing a volatile memory die.
• In response to initializing the volatile memory die, a first non-volatile memory die is initialized.
• Executable instructions are then copied from the first non-volatile memory die to the volatile memory die.
• After initializing the first non-volatile memory die, a second non-volatile memory die is initialized.
• If an error occurs during the initialization of the second non-volatile memory die, a failure record is stored in the first non-volatile memory die.

Potential applications of this technology:

• This technology can be used in various electronic devices that utilize non-volatile memory, such as computers, smartphones, and tablets.
• It can be particularly useful in systems where multiple non-volatile memory dies are used, ensuring that initialization failures are properly recorded.

Problems solved by this technology:

• The method addresses the issue of non-volatile memory initialization failures by providing a mechanism to store failure records.
• By storing failure records, it becomes easier to identify and diagnose initialization errors, allowing for more efficient troubleshooting and maintenance.

Benefits of this technology:

• The method ensures that failure records are stored in a reliable and accessible manner, facilitating the identification and resolution of initialization errors.
• By copying executable instructions from the first non-volatile memory die to the volatile memory die, the method ensures that the system can continue functioning even if there are initialization failures in the second non-volatile memory die.
• This technology improves the overall reliability and stability of systems that rely on non-volatile memory.

Abstract

The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.

APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME (17938307)

Main Inventor

Murong Lang

Brief explanation

The patent application describes methods, apparatuses, and systems for managing deck-specific read levels in a memory array. 

• The apparatus includes a memory array with memory cells organized into two or more decks.
• The apparatus can determine a delay between programming the decks.
• The apparatus can adjust a base read level with an offset level based on the delay and/or the targeted read location.
• The deck-specific read levels are derived and implemented by selectively adjusting the base read level.

Potential Applications

• Memory management in electronic devices
• Data storage and retrieval in computer systems
• Improving performance and efficiency of memory arrays

Problems Solved

• Ensuring accurate and reliable reading of data from memory cells
• Optimizing read levels based on specific decks and targeted read locations
• Managing delays between programming decks to minimize errors

Benefits

• Improved data accuracy and reliability
• Enhanced performance and efficiency of memory arrays
• Customized read levels for different decks and read locations

Abstract

Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

SAFE AREA FOR CRITICAL CONTROL DATA (18205036)

Main Inventor

Aleksei Vlasov

Brief explanation

The abstract describes a method for ensuring the safety of information in a computing system during power events. Here is a simplified explanation of the abstract:

• The method involves writing information about the state of a computing system to a secure area of a memory sub-system within the system.
• If a power event occurs, the method detects it and takes action.
• In response to the power event, the method either writes the information from the secure area to a persistent memory area or retrieves it from the persistent memory area.

Potential Applications

This technology can be applied in various fields where data integrity and system reliability are crucial, including:

• Data centers and server farms
• Industrial control systems
• Autonomous vehicles
• Aerospace and defense systems
• Medical devices

Problems Solved

The method addresses the following problems:

• Data loss during power events: By writing information to a safe area and then transferring it to a persistent memory area, the method ensures that critical data is not lost in the event of a power failure.
• System stability: By retrieving the information from the persistent memory area after a power event, the method helps restore the system to its previous state, minimizing disruptions and potential errors.

Benefits

The use of this method offers several benefits:

• Data protection: The information stored in the safe area is safeguarded against power events, reducing the risk of data loss and corruption.
• System resilience: By retrieving the information from the persistent memory area, the method helps maintain system stability and continuity, even after power interruptions.
• Improved reliability: The method enhances the overall reliability of computing systems by providing a mechanism for preserving critical data during power events.

Abstract

A method includes writing information comprising a state of a computing system to a safe area of a memory sub-system that is deployed within the computing system. The method further includes determining that a power event involving the computing system has occurred. The method further includes causing, responsive to the determination that the power event has occurred, the information written to the safe area of the memory sub-system to be written to or retrieved from a persistent memory area of the memory sub-system.

VERIFIED KEY REPLACEMENT IN SECURE MEMORY DEVICES (17831370)

Main Inventor

Zhan Liu

Brief explanation

The patent application describes a method for delivering cryptographic data to secure memory devices. 

• The method involves receiving a command by a memory device, which includes a public key and a hash of a unique device secret (UDS).
• The memory device generates a local UDS using the public key and a locally stored private key.
• It then generates a local UDS hash by inputting the local UDS into a hashing algorithm.
• The memory device determines whether the local UDS hash matches the hash included in the command.
• If there is a match, the memory device writes the public key to a key storage area.
• If there is no match, the memory device returns a failure response.

Potential Applications:

• This technology can be applied in various secure memory devices, such as smart cards, secure USB drives, or secure embedded systems.
• It can be used in systems that require secure storage and retrieval of cryptographic data, such as authentication systems, secure communication systems, or secure payment systems.

Problems Solved:

• The method ensures the secure delivery of cryptographic data to memory devices by verifying the integrity of the received data.
• It prevents unauthorized access to the memory device by ensuring that only valid commands with matching hashes are processed.

Benefits:

• The method provides a secure and efficient way to deliver cryptographic data to memory devices.
• It enhances the security of memory devices by verifying the integrity of the received data.
• It simplifies the process of storing and retrieving cryptographic keys in memory devices.

Abstract

The disclosure relates to improvements in the delivery of cryptographic data to secure memory devices. In some aspects, the techniques described herein relate to a method including: receiving, by a memory device, a command, the command including a public key and a hash of a unique device secret (UDS); generating, by the memory device, a local UDS using the public key and a locally stored private key; generating, by the memory device, a local UDS hash by inputting the local UDS into a hashing algorithm; determining, by the memory device, whether the local UDS hash matches the hash included in the command; writing, by the memory device, the public key to a key storage area if the local UDS hash matches the hash included in the command; and returning, by the memory device, a failure response if the local UDS hash does not match the hash included in the command.

PROTECTION AGAINST INVALID MEMORY COMMANDS (17834547)

Main Inventor

Sourin SARKAR

Brief explanation

The patent application describes a method for protecting against invalid memory commands. Here are the key points:

• The memory device receives a pilot command from a host device, which indicates a sequence of upcoming memory commands.
• After receiving the pilot command, the memory device receives a memory command from the host device.
• The memory device determines if the memory command is invalid based on the indication of the sequence of upcoming memory commands.
• If the memory command is determined to be invalid, the memory device transmits a message to the host device indicating the invalidity of the memory command.

Potential applications of this technology:

• This technology can be used in various memory devices such as solid-state drives (SSDs), random-access memory (RAM), and flash memory.
• It can be implemented in computer systems, servers, and other devices that use memory commands.

Problems solved by this technology:

• Invalid memory commands can cause data corruption, system crashes, and other issues. This technology helps prevent such problems by identifying and rejecting invalid memory commands.

Benefits of this technology:

• Improved system reliability and stability by preventing the execution of invalid memory commands.
• Protection against potential security vulnerabilities that may arise from executing invalid memory commands.
• Enhanced performance by avoiding unnecessary processing of invalid memory commands.

Abstract

Implementations described herein relate to protection against invalid memory commands. In some implementations, a memory device may include one or more components that may receive, from a host device, a pilot command that includes an indication of a sequence of upcoming memory commands to be transmitted from the host device to the memory device, receive a memory command from the host device after receiving the pilot command, determine that the memory command is invalid based on the indication of the sequence of upcoming memory commands, and transmit, to the host device and based on determining that the memory command is invalid, a message indicating that the memory command is invalid. Numerous other implementations are described.

POWER EFFICIENT CODEWORD SCRAMBLING IN A NON-VOLATILE MEMORY DEVICE (17829920)

Main Inventor

Eyal En Gad

Brief explanation

The abstract describes a patent application for a processing device in a memory sub-system that performs memory access operations using a randomized string generated from a hashed seed.

• The processing device receives a request to perform a memory access operation on a memory device.
• It determines a memory segment identifier associated with the memory access operation.
• A hash function is applied to the memory segment identifier to generate a hashed seed.
• The hashed seed is provided to a pseudo-random number generator.
• The pseudo-random number generator generates a randomized string.
• The memory access operation is performed on the memory device using the randomized string.

Potential Applications

• This technology can be applied in various memory sub-systems, such as computer systems, servers, and data centers.
• It can be used in any application that requires memory access operations, including data storage, retrieval, and processing.

Problems Solved

• This technology solves the problem of predictable memory access patterns, which can be exploited by malicious actors.
• By generating a randomized string, it adds an additional layer of security to memory access operations, making it harder for attackers to predict and exploit.

Benefits

• Improved security: The use of randomized strings makes it more difficult for attackers to predict and exploit memory access operations.
• Enhanced privacy: The randomized strings add an extra level of privacy by making it harder for unauthorized users to access and manipulate memory data.
• Increased performance: By randomizing memory access operations, this technology can potentially improve overall system performance by distributing memory requests more evenly.

Abstract

A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS (17823371)

Main Inventor

Ferdinando Bedeschi

Brief explanation

Methods, systems, and devices for transistor configurations for vertical memory arrays are described in this patent application. The memory device implements a multi-transistor architecture, specifically a two-transistor architecture, to connect pillars with bit lines. Here is a simplified explanation of the abstract:

• The memory device includes a conductive pillar that extends through different levels of the memory array.
• The pillar is connected to a first bit line through a first transistor and to a second bit line through a second transistor.
• To access a memory cell connected to the pillar, the memory device biases a word line connected to the memory cell to a first access voltage.
• One of the bit lines is biased to a second access voltage, and one of the transistors is activated to connect the pillar with that bit line.
• The other transistor is deactivated to isolate the pillar from the other bit line.

Potential Applications

This technology has potential applications in various fields, including:

• Memory devices and systems
• Semiconductor manufacturing
• Data storage and retrieval systems

Problems Solved

The patent addresses the following problems:

• Efficiently connecting conductive pillars with bit lines in a vertical memory array
• Enabling access to specific memory cells in the array
• Isolating the conductive pillars from unwanted bit lines

Benefits

The benefits of this technology include:

• Improved performance and efficiency of memory devices
• Enhanced data storage and retrieval capabilities
• Simplified transistor configurations for vertical memory arrays

Abstract

Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION (17946518)

Main Inventor

Yang Lu

Brief explanation

The abstract describes a system for enhancing the security and reliability of memory devices by mitigating the effects of row hammer attacks. Row hammer is a vulnerability in dynamic random access memory (DRAM) that allows an attacker to manipulate data by rapidly accessing and deactivating specific rows of memory cells.

• The system includes a control mechanism implemented in the front-end and/or back-end of a memory sub-system.
• The control mechanism refreshes rows of memory to prevent row hammer attacks.
• A row activation command is received by the control circuitry, which increments a row counter stored in a content addressable memory (CAM).
• The control circuitry determines if the row counter exceeds a row hammer threshold (RHT) minus a counter for CAM decrease (CDC).
• The CDC is incremented each time the CAM is full.
• If the row counter exceeds the RHT minus the CDC, a refresh command is issued to the corresponding row address.

Potential applications of this technology:

• Memory devices in computers, servers, and other electronic devices can benefit from enhanced security and reliability.
• Cloud computing infrastructure can utilize this technology to protect against row hammer attacks and improve data integrity.
• Mobile devices, such as smartphones and tablets, can benefit from the mitigation of row hammer vulnerabilities.

Problems solved by this technology:

• Row hammer attacks can manipulate data and compromise the security and integrity of memory devices.
• Row hammer vulnerabilities can lead to system crashes, data corruption, and unauthorized access.
• Existing mitigation techniques may not be sufficient to prevent row hammer attacks.

Benefits of this technology:

• Enhanced security: By mitigating row hammer attacks, the system improves the security of memory devices and protects against unauthorized data manipulation.
• Improved reliability: Refreshing rows of memory reduces the likelihood of data corruption and system crashes caused by row hammer vulnerabilities.
• Compatibility: The control mechanism can be implemented in existing memory sub-systems without requiring significant hardware or software modifications.

Abstract

Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

TEST MODE STATE MACHINE FOR A MEMORY DEVICE (17830169)

Main Inventor

Rucha Deepak Geedh

Brief explanation

The patent application describes a memory device that is capable of self-testing using test mode state machines. The memory device includes a memory array with memory cells and periphery logic that receives a command from a host device to initiate self-testing. The periphery logic generates trigger signals in response to the command. The memory device also includes control circuitry with state machines that receive the trigger signals and execute a command sequence, which includes read, write, or delay operations. Each partition of the memory array can have its own integrated state machine.

• Memory device with self-testing capabilities using test mode state machines
• Memory array with memory cells and periphery logic
• Periphery logic receives a command from a host device to initiate self-testing
• Periphery logic generates trigger signals in response to the command
• Control circuitry with state machines receives the trigger signals and executes a command sequence
• Command sequence includes read, write, or delay operations
• Each partition of the memory array can have its own integrated state machine

Potential Applications

• Memory devices used in various electronic devices such as computers, smartphones, and tablets
• Testing and quality control of memory devices during manufacturing process

Problems Solved

• Provides a self-testing mechanism for memory devices, reducing the need for external testing equipment
• Allows for efficient and automated testing of memory devices during manufacturing process

Benefits

• Simplifies the testing process for memory devices
• Reduces the cost and time associated with external testing equipment
• Improves the overall quality and reliability of memory devices

Abstract

Systems, methods, and apparatus for a memory device having test mode state machines configured to perform self-testing. In one approach, a memory array has memory cells. Periphery logic of the memory device receives a command from a host device to initiate self-testing. The periphery logic generates trigger signal(s) in response to receiving the command. Control circuitry (e.g., a controller) has state machine(s) that receives the trigger signal(s) and initiates execution of a command sequence. The command sequence includes various orders of operations such as read, write, or delay. A state machine can be integrated into each of multiple partitions of the memory array.

ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE (17830625)

Main Inventor

Zhenming Zhou

Brief explanation

The patent application describes a system that includes a memory device and a processing device. The system performs operations to improve the reliability and performance of the memory device.

• The system receives a request to read a specific segment of the memory device.
• It determines the program erase cycle count associated with the segment, which indicates the number of times the segment has been programmed and erased.
• The system also determines a temperature offset value for the segment based on the write temperature and read temperature.
• It checks whether the temperature offset value meets a threshold criterion associated with the program erase cycle count.
• If the temperature offset value satisfies the threshold criterion, the system performs a corrective read operation on the segment.
• The sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

Potential applications of this technology:

• This technology can be used in various memory devices, such as flash memory, to improve their reliability and performance.
• It can be implemented in devices like smartphones, tablets, and computers to enhance the overall user experience.

Problems solved by this technology:

• Memory devices can experience errors and performance degradation over time due to repeated programming and erasing.
• Temperature variations can further impact the reliability and performance of memory devices.
• This technology addresses these issues by performing corrective read operations based on temperature offset values and program erase cycle counts.

Benefits of this technology:

• By performing corrective read operations, the system can mitigate errors and improve the accuracy of data retrieval from memory devices.
• The modification of the sense time parameter based on temperature offset values and program erase cycle counts helps optimize the read operation for better performance.
• This technology enhances the overall reliability and lifespan of memory devices, leading to improved user satisfaction and reduced data loss.

Abstract

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES (17830802)

Main Inventor

Yu-Chung Lien

Brief explanation

The abstract describes a method for optimizing memory page scans in a computer system. 

• The method starts by performing a first page read on the first memory page using a first trim value.
• It then determines if the first data state metric associated with the first page read meets a certain threshold criterion.
• If the criterion is met, a second page read is performed on the first memory page using a second trim value.
• The method then determines if the second data state metric associated with the second page read meets a second threshold criterion.
• If the second criterion is not met, the second trim value is selected for subsequent page reads during memory page scans.

Potential applications of this technology:

• This method can be used in computer systems that perform memory page scans, such as operating systems or database management systems.
• It can help optimize the scanning process by selecting the most appropriate trim value for page reads based on data state metrics.

Problems solved by this technology:

• Memory page scans can be time-consuming and resource-intensive.
• This method helps improve the efficiency of memory page scans by selecting the optimal trim value for page reads.

Benefits of this technology:

• By selecting the most suitable trim value, the method reduces the time and resources required for memory page scans.
• It improves the overall performance and efficiency of computer systems that rely on memory page scans.

Abstract

A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

PLANE BALANCING IN A MEMORY SYSTEM (17864192)

Main Inventor

John J. Kane

Brief explanation

Methods, systems, and devices for plane balancing in a memory system are described in this patent application. The memory system selects a memory die for writing a set of data, which consists of a plurality of planes, each containing multiple blocks of memory cells. The memory system determines the availability status of blocks in two different planes and writes the data to the planes based on the quantity of available blocks.

• The memory system selects a memory die for writing data.
• The memory die consists of multiple planes, each containing blocks of memory cells.
• The memory system determines the availability status of blocks in two different planes.
• The system writes the data to the planes, excluding the plane with the highest quantity of blocks with the availability status.
• The decision of which planes to write the data to is based on the quantity of available blocks in each plane.

Potential Applications

• Memory systems in electronic devices such as smartphones, tablets, and computers.
• Data storage systems in servers and data centers.

Problems Solved

• Balancing the usage of memory planes in a memory system.
• Preventing overuse of specific planes, which can lead to performance degradation and reduced lifespan of the memory system.

Benefits

• Improved performance and reliability of memory systems.
• Extended lifespan of memory systems by evenly distributing the usage across planes.
• Efficient utilization of memory resources.

Abstract

Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

MEMORY CONTROLLER FIRMWARE VIRTUALIZATION (17899900)

Main Inventor

Niccolò Izzo

Brief explanation

The abstract of this patent application describes a device that includes a datapath, a firmware storage device, and a processor with a hypervisor. The hypervisor is designed to execute firmware tasks in a container and control access to the datapath based on tags associated with instructions of the firmware tasks.

• The device includes a datapath that facilitates data transfers between a host device and a storage device.
• A firmware storage device is present, which stores multiple firmware tasks.
• The processor of the device includes a hypervisor that executes a specific firmware task in a container.
• The hypervisor also controls access to the datapath based on tags associated with instructions of the firmware task.

Potential Applications

• This technology can be applied in storage devices, such as solid-state drives (SSDs) or hard disk drives (HDDs), to enhance data transfer efficiency and security.
• It can be used in virtualized environments to improve the performance and security of data transfers between host devices and storage devices.
• The device can find applications in cloud computing environments where efficient and secure data transfers are crucial.

Problems Solved

• The technology addresses the problem of inefficient data transfers between host devices and storage devices by optimizing the datapath and executing firmware tasks in a container.
• It solves the problem of security vulnerabilities in data transfers by controlling access to the datapath based on tags associated with firmware task instructions.

Benefits

• The device improves data transfer efficiency by optimizing the datapath and executing firmware tasks in a container.
• It enhances security by controlling access to the datapath based on tags associated with firmware task instructions.
• The technology can lead to faster and more secure data transfers in various computing environments.

Abstract

In some aspects, the techniques described herein relate to a device including: a datapath facilitating data transfers between a host device and a storage device; a firmware storage device storing a plurality of firmware tasks; and a processor, the processor including a hypervisor configured to: execute a given firmware task in the plurality of firmware tasks in a container, and control access to the datapath based on tags associated with instructions of the given firmware task.

ACCESS HEATMAP GENERATION AT A MEMORY DEVICE (17831270)

Main Inventor

Nabeel Meeramohideen Mohamed

Brief explanation

The patent application describes methods, systems, and devices for generating access heatmaps in a memory device. Here are the key points:

• The memory device maintains a register to track access operations, where each access operation of a memory address is mapped to multiple fields of the register.
• When a first access operation occurs on a first address, the memory device increments both a first field and a second field of the register.
• When a second access operation occurs on a second address, the memory device increments the first field and a third field of the register.
• The memory device also maintains a second register with fields indicating addresses where access occurrences meet a threshold.

Potential applications of this technology:

• Memory optimization: The access heatmaps can provide valuable insights into the usage patterns of memory addresses, allowing for better memory allocation and optimization.
• Performance analysis: By analyzing the access heatmaps, system designers can identify hotspots and bottlenecks in memory access, enabling them to make improvements for better performance.
• Cache management: The heatmaps can help in determining which memory addresses should be cached for faster access, improving overall system efficiency.

Problems solved by this technology:

• Lack of visibility: Traditional memory devices do not provide detailed information about access patterns, making it challenging to optimize memory usage and identify performance issues.
• Inefficient memory allocation: Without access heatmaps, memory may be allocated inefficiently, leading to wasted resources and potential performance degradation.
• Difficulty in cache management: Without insights into access patterns, it is difficult to determine which memory addresses should be cached, resulting in suboptimal cache utilization.

Benefits of this technology:

• Improved memory utilization: Access heatmaps enable better allocation of memory resources, reducing wastage and improving overall system efficiency.
• Enhanced performance: By identifying hotspots and bottlenecks, system designers can make targeted optimizations to improve memory access performance.
• Efficient cache management: With access heatmaps, cache management becomes more effective, leading to faster access times and improved system responsiveness.

Abstract

Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

DATA PATH SEQUENCING IN MEMORY SYSTEMS (17832068)

Main Inventor

Rohitkumar Makhija

Brief explanation

The abstract describes systems and methods for data path scheduling in memory systems. The system includes a memory array and a controller. The controller performs operations such as retrieving a memory access command, identifying the specified memory device, verifying its availability, verifying availability of required resources, transmitting the command to the memory device, and removing the command from the queue.

• The system is designed to schedule data paths in memory systems.
• It includes a memory array with multiple memory cells.
• The controller is responsible for managing memory access commands.
• It retrieves commands from a queue and identifies the specified memory device.
• The availability of the memory device and required resources is verified.
• The command is then transmitted to the memory device.
• Once the command is processed, it is removed from the queue.

Potential Applications

• This technology can be applied in various memory systems, such as computer memory, storage devices, and embedded systems.
• It can improve the efficiency and performance of memory access operations in these systems.

Problems Solved

• The system solves the problem of efficiently scheduling data paths in memory systems.
• It ensures that memory access commands are properly managed and executed.
• It helps prevent conflicts and delays in accessing memory devices.

Benefits

• The system improves the overall performance and efficiency of memory systems.
• It allows for better utilization of memory resources.
• It helps reduce access delays and conflicts, leading to faster data retrieval and processing.

Abstract

Described are systems and methods for data path scheduling in memory systems. An example system comprises: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array, the controller to perform operations comprising: retrieving a memory access command from a memory access command queue; identifying a memory device specified by the memory access command; verifying availability of the memory device; verifying availability of one or more resources that are required for servicing the memory access command; transmitting the memory access command to the memory device; and removing the memory access command from the memory access command queue.

APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS (18331746)

Main Inventor

Perry V. Lea

Brief explanation

The abstract describes an invention related to in-memory operations, specifically for a PIM (Processing-In-Memory) capable device. The device includes an array of memory cells and sensing circuitry, which includes a sense amplifier and a compute component. The device also includes timing circuitry and a sequencer to control the timing and coordination of compute operations. The sequencer receives command instructions from an external source to initiate compute operations.

• PIM capable device with memory cells and sensing circuitry
• Sensing circuitry includes a sense amplifier and a compute component
• Timing circuitry controls the timing of operations performed using the sensing circuitry
• Sequencer coordinates compute operations
• Sequencer receives command instructions from an external source to initiate compute operations

Potential Applications

• High-performance computing
• Artificial intelligence and machine learning
• Data analytics and processing
• Real-time processing and decision-making systems

Problems Solved

• Improved performance and efficiency of in-memory operations
• Reduced latency in compute operations
• Enhanced coordination and control of compute operations

Benefits

• Faster and more efficient processing of data
• Lower power consumption
• Improved scalability and parallelism in computing tasks
• Real-time processing capabilities

Abstract

Apparatuses and methods are provided for in-memory operations. An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.

DATA PROTECTION FOR STACKS OF MEMORY DICE (17831263)

Main Inventor

Marco Sforzin

Brief explanation

The patent application describes a method for connecting memory dice in a stack, both externally and internally, to act as interface dice for other memory dice.

• Memory dice in a stack can be connected externally or internally.
• External connections serve as interface dice for internally connected memory dice.
• Data protection and recovery schemes are based on a single data stream without discontinuity between transfers.
• Simplified explanation: The patent application proposes a way to connect memory dice in a stack, allowing for efficient data transfer and protection.

Potential Applications

This technology has potential applications in various fields, including:

• Computer memory systems
• Data storage devices
• High-performance computing
• Artificial intelligence systems

Problems Solved

The technology addresses the following problems:

• Efficient data transfer between memory dice in a stack
• Data protection and recovery schemes for memory dice stacks
• Streamlining the connection process for memory dice

Benefits

The benefits of this technology include:

• Improved data transfer speed and efficiency
• Enhanced data protection and recovery capabilities
• Simplified connection process for memory dice stacks
• Potential for increased performance in memory systems and data storage devices

Abstract

Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.

APPARATUS WITH DYNAMIC ARBITRATION MECHANISM AND METHODS FOR OPERATING THE SAME (17937358)

Main Inventor

John E. Maroney

Brief explanation

The abstract of this patent application describes methods, apparatuses, and systems for dynamically controlling the flow and implementation of operations for each function. The apparatus utilizes a timing parameter to initiate the execution of queued commands. It includes a queue arbiter that can adjust the timing for each function based on feedback received regarding the resources consumed in implementing preceding commands for that particular function.

• The patent application focuses on dynamically controlling the flow and implementation of operations for each function.
• It introduces the use of a timing parameter to initiate the execution of queued commands.
• The apparatus includes a queue arbiter that can dynamically adjust the timing for each function based on feedback received.
• The feedback corresponds to the resources consumed in implementing preceding commands for the corresponding function.

Potential Applications

• This technology can be applied in various fields where dynamic control of operations is required, such as computer systems, network infrastructure, and industrial automation.
• It can be used in cloud computing environments to optimize resource allocation and improve overall system performance.
• The technology can be implemented in robotics and autonomous systems to enhance their ability to adapt and respond to changing conditions.

Problems Solved

• The technology addresses the challenge of efficiently managing the flow and implementation of operations for different functions.
• It solves the problem of resource allocation by dynamically adjusting the timing for each function based on the resources consumed in implementing preceding commands.
• The patent application provides a solution for optimizing the execution of queued commands and improving overall system efficiency.

Benefits

• The dynamic control of operations allows for better resource utilization and improved system performance.
• By adjusting the timing for each function based on resource feedback, the technology ensures efficient allocation of resources.
• The implementation of queued commands is optimized, leading to faster and more effective execution of operations.

Abstract

Methods, apparatuses and systems related to dynamically controlling flow and implementation of operations for each function. The apparatus may use a timing parameter to initiate implementation of queued commands. The apparatus may include a queue arbiter configured to dynamically adjust the timing for each function according to a feedback that corresponds to resources consumed in implementing preceding commands for the corresponding function.

PRIORITIZATION OF SUCCESSFUL READ RECOVERY OPERATIONS FOR A MEMORY DEVICE (17809731)

Main Inventor

Naveen BOLISETTY

Brief explanation

The patent application describes a method for recovering from read failures in a memory device. Here are the key points:

• The memory device detects a read failure in a specific page type and memory section.
• It performs multiple read recovery operations in a predefined order to try and recover from the failure.
• If one of the recovery operations is successful, the device reorders the sequence of recovery operations to prioritize the successful one.
• The memory device then detects a second read failure in the same page type and memory section.
• It performs read recovery operations in the new order to recover from the second failure.

Potential applications of this technology:

• Memory devices in computers, smartphones, and other electronic devices can benefit from improved read recovery methods.
• Data centers and cloud computing facilities can use this technology to enhance the reliability and performance of their memory systems.

Problems solved by this technology:

• Read failures in memory devices can lead to data loss and system instability. This technology provides a method to recover from such failures and ensure data integrity.
• By prioritizing successful recovery operations, the memory device can optimize its performance and reduce the time required for recovery.

Benefits of this technology:

• Improved reliability: The memory device can recover from read failures, reducing the risk of data loss and system crashes.
• Enhanced performance: By prioritizing successful recovery operations, the memory device can recover more efficiently and minimize downtime.
• Increased data integrity: The technology ensures that data stored in the memory device remains intact and can be accessed reliably.

Abstract

In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION (17858731)

Main Inventor

Charles See Yeung Kwong

Brief explanation

The abstract describes a method for managing the reliability of memory devices by identifying blocks within the memory and associating them with a capability metric that reflects the projected reliability of the underlying components. If the capability metric meets a certain condition, a cycle threshold is determined for the block. When the program/erase cycle counter reaches the cycle threshold, the block is excluded from the set of blocks and a program operation is performed on the updated set.

• Identifying blocks of a memory device and associating them with a capability metric reflecting the projected reliability of the underlying components.
• Determining a cycle threshold for a block based on the capability metric.
• Updating the set of blocks by excluding a block when the program/erase cycle counter matches the cycle threshold.
• Performing a program operation on the updated set of blocks.

Potential Applications

• Memory management in electronic devices.
• Improving the reliability and lifespan of memory devices.

Problems Solved

• Ensuring the reliability of memory devices by monitoring and managing the program/erase cycles.
• Optimizing the use of memory blocks based on their projected reliability.

Benefits

• Increased reliability and lifespan of memory devices.
• Efficient utilization of memory blocks.
• Improved performance and longevity of electronic devices.

Abstract

A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.

ERROR HANDLING (17965909)

Main Inventor

Sampath K. Ratnam

Brief explanation

The abstract of the patent application describes a method for handling errors in a memory device based on media management data. Here is a simplified explanation of the abstract:

• Error handling flags are set based on media management data of a memory device.
• The system determines if any of the error handling flags are set.
• If at least one flag is set, a subset of operations from an error handling flow associated with the set flags is performed.

Potential Applications:

• Memory devices such as solid-state drives (SSDs) or flash drives.
• Data storage systems.
• Embedded systems with memory management.

Problems Solved:

• Efficient error handling in memory devices.
• Improved reliability and data integrity.
• Streamlined error handling process.

Benefits:

• Enhanced error detection and correction capabilities.
• Reduced risk of data loss or corruption.
• Improved performance and reliability of memory devices.

Abstract

Respective error handling (EH) flags can be set based at least in part on media management data of a memory device. Whether any of the EH flags are set can be determined. In response to determining that at least one of the EH flags is set, a subset of a plurality of operations of an EH flow associated with the set EH flags can be performed.

System And Method To Control Memory Error Detection With Automatic Disabling (17829576)

Main Inventor

Thanh K. Mai

Brief explanation

The abstract describes a memory device that includes a command interface, an input output interface, and error detection circuitry. The error detection circuitry generates signals based on different periods of time and clock signals to make determinations about data signals.

• The memory device has a command interface to receive write commands.
• It also has an input output interface to receive data signals along with the write command.
• The error detection circuitry is connected to the input output interface.
• The error detection circuitry generates a first signal to determine a first portion of the data signals using a first data strobe signal as a clock.
• It also generates a second signal to determine a second portion of the data signals using a second data strobe signal as a clock.
• The error detection circuitry generates a control signal based on the first signal, the second signal, and the slower of the two data strobe signals.

Potential Applications

• This memory device can be used in various electronic devices that require reliable and accurate data storage and retrieval.
• It can be implemented in computer systems, servers, mobile devices, and other electronic devices that use memory for data storage.

Problems Solved

• The error detection circuitry helps in identifying and correcting errors in the data signals received by the memory device.
• By using different clock signals and periods of time, the memory device can accurately determine and handle different portions of the data signals.

Benefits

• The memory device provides improved error detection and correction capabilities, ensuring data integrity.
• It allows for efficient and reliable data storage and retrieval.
• The use of different clock signals and periods of time enhances the accuracy and efficiency of data processing in the memory device.

Abstract

A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

MEMORY SUB-SYSTEM ADDRESSING FOR DATA AND ADDITIONAL DATA PORTIONS (17831436)

Main Inventor

Daniele Balluchi

Brief explanation

The abstract describes a system and method for addressing data and additional data portions in a memory device. It involves converting a command received in a non-deterministic memory interface protocol to a standardized deterministic memory interface protocol, and accessing the memory cells using the converted address.

• The method involves accessing data written to a memory device in response to a compute express link (CXL) protocol compliant command.
• The address associated with the command is converted to a DRAM accessible command according to a standardized deterministic memory interface protocol.
• A page of memory cells is accessed using the converted address, where the data and additional data portions are written.

Potential Applications

• This technology can be applied in various computing systems that utilize memory devices, such as servers, data centers, and high-performance computing systems.
• It can improve the efficiency and performance of memory access in these systems, enabling faster data processing and improved overall system performance.

Problems Solved

• Non-deterministic memory interface protocols can pose challenges in accessing and managing data in memory devices.
• Converting the commands to a standardized deterministic memory interface protocol solves the problem of compatibility and allows for efficient access to memory cells.

Benefits

• The conversion of commands allows for seamless integration of memory devices with different interface protocols.
• It enables faster and more efficient memory access, improving overall system performance.
• The technology provides a standardized approach to addressing data and additional data portions, simplifying memory management in computing systems.

Abstract

Systems, apparatuses, and methods related to addressing for data and additional data portions are described herein. In an example method, addressing for data and additional data portions can include accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol. The first command can be a compute express link (CXL) protocol compliant command. The example method can further include converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol. The second command can be a DRAM accessible command. The example method can further include accessing a page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the converted address associated with the first command.

Error Detection in Communications over Serial Peripheral Interfaces (17834414)

Main Inventor

Minjian Wu

Brief explanation

The abstract describes a memory device and a host system that use serial peripheral interfaces to transmit data. The data is followed by a cyclic redundancy check (CRC) value, which is used to verify the accuracy of the data transmission. If the received CRC value does not match the computed CRC value, an interrupt signal is sent to request re-transmission of the data.

• The memory device and host system use serial peripheral interfaces to transmit data and CRC values.
• The CRC value is used to check the accuracy of the data transmission.
• If the received CRC value does not match the computed CRC value, an interrupt signal is sent to request re-transmission.
• The host system can terminate a read command and re-transmit it if a transmission error is detected.

Potential Applications

• This technology can be used in various memory devices and host systems that utilize serial peripheral interfaces.
• It can be applied in systems where data integrity is crucial, such as in communication devices, storage devices, and embedded systems.

Problems Solved

• Ensures the accuracy of data transmission by using CRC values to detect errors.
• Provides a mechanism for requesting re-transmission of data when errors are detected.
• Allows the host system to terminate and re-transmit commands in case of transmission errors.

Benefits

• Improved data integrity by verifying the accuracy of data transmission.
• Efficient error detection and re-transmission mechanism.
• Enhances the reliability and performance of memory devices and host systems.

Abstract

A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.

MANAGING DATA INTEGRITY USING A CHANGE IN A NUMBER OF DATA ERRORS AND AN AMOUNT OF TIME IN WHICH THE CHANGE OCCURRED (17831086)

Main Inventor

Ryan G. Fisher

Brief explanation

The patent application describes methods, apparatuses, and systems for monitoring and maintaining data integrity in memory systems. Here is a simplified explanation of the abstract:

• An initial data integrity scan is performed on a subset of memory to determine the error rate at a specific time.
• The initial error rate and time are stored for reference.
• A subsequent integrity scan is conducted on the same subset of memory at a later time to determine the new error rate.
• The difference between the initial and subsequent error rates is calculated.
• The difference between the initial and subsequent times is determined.
• Based on these differences, a remedial action is selected and executed to address any detected errors.

Potential applications of this technology:

• Memory systems in computer hardware and electronic devices.
• Data storage systems in cloud computing and data centers.
• Embedded systems and IoT devices with limited memory capacity.

Problems solved by this technology:

• Ensuring data integrity in memory systems by detecting and addressing errors.
• Preventing data corruption and loss due to memory errors.
• Improving the reliability and performance of memory systems.

Benefits of this technology:

• Early detection and correction of memory errors.
• Improved data reliability and integrity.
• Enhanced system performance and uptime.
• Cost savings by avoiding data loss and system failures.

Abstract

Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE (17804826)

Main Inventor

Nitul Gohain

Brief explanation

The patent application describes methods, systems, and devices for determining memory locations for boot-up code. It involves receiving an indication of timeout durations for a boot sequence and storing information for the boot sequence in memory cells based on these durations. The selection of memory cells is based on factors such as read latency, error rate, and storage-level. The stored information is accessed during the initialization of the boot sequence.

• The patent application focuses on determining memory locations for boot-up code.
• It involves receiving timeout durations for a boot sequence.
• Information for the boot sequence is stored in memory cells based on the timeout durations.
• The selection of memory cells is based on factors like read latency, error rate, and storage-level.
• The stored information is accessed during the initialization of the boot sequence.

Potential Applications

This technology has potential applications in various fields, including:

• Computer systems and servers
• Embedded systems and IoT devices
• Mobile devices and smartphones
• Automotive electronics and infotainment systems
• Industrial control systems and automation

Problems Solved

The technology addresses the following problems:

• Efficient determination of memory locations for boot-up code
• Optimizing storage and retrieval of boot sequence information
• Minimizing read latency and error rates during boot-up
• Enhancing the reliability and performance of boot sequences

Benefits

The technology offers several benefits, including:

• Improved boot-up speed and efficiency
• Enhanced reliability and error handling during boot sequences
• Optimal utilization of memory cells based on timeout durations
• Increased performance and responsiveness of systems during initialization.

Abstract

Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.

EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC (17807813)

Main Inventor

Scott E. Schaefer

Brief explanation

Methods, systems, and devices for evaluating the health of memory devices are described in this patent application. The memory device includes health monitoring logic that activates internal health monitors and communicates their output. 

• The health monitoring logic can operate in two modes:

 * In the first mode, it provides a single output generated from multiple outputs of the set of monitors. 
 * In the second mode, it cycles through certain monitors (in a test mode) and generates an output corresponding to each active monitor as it cycles through them. 

• The health monitoring logic communicates the output of each monitor to a host device, allowing the host device to evaluate the output from each monitor of the set.

Potential Applications

This technology has potential applications in various industries and fields, including:

• Memory device manufacturing: The evaluation of memory device health can help identify any issues or defects during the manufacturing process, ensuring the production of high-quality memory devices.
• Data centers: Memory device health monitoring can be crucial in data centers to detect any potential failures or malfunctions in memory devices, allowing for proactive maintenance and minimizing downtime.
• Consumer electronics: This technology can be utilized in consumer electronic devices, such as smartphones and laptops, to monitor the health of memory devices and provide early warnings of any potential issues.

Problems Solved

The technology described in this patent application addresses several problems related to memory device health monitoring:

• Efficient evaluation: By providing a single output or cycling through active monitors, the health monitoring logic simplifies the evaluation process, making it more efficient and less time-consuming.
• Comprehensive monitoring: The activation of multiple internal health monitors ensures a comprehensive evaluation of the memory device's health, allowing for the detection of various potential issues.
• Easy integration: The communication of monitor outputs to a host device enables easy integration with existing systems and facilitates the evaluation of memory device health.

Benefits

The use of this technology offers several benefits:

• Early detection of issues: By continuously monitoring the health of memory devices, potential issues can be detected early, allowing for timely maintenance or replacement, thus reducing the risk of data loss or system failures.
• Improved reliability: Regular evaluation of memory device health ensures that only reliable devices are used, minimizing the chances of unexpected failures and improving overall system reliability.
• Cost savings: Proactive maintenance and early detection of issues can help prevent costly downtime and data loss, resulting in significant cost savings for businesses and consumers.

Abstract

Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

CROSS-TEMPERATURE COMPENSATION IN NON-VOLATILE MEMORY DEVICES (17830800)

Main Inventor

Andrea Giovanni Xotta

Brief explanation

The patent application describes a system and method for improving the read operation of a memory device based on the temperature at which the data was written. 

• The system includes a memory device and a processing device.
• The processing device performs a first read operation on the memory device to retrieve data.
• The first data contains information about the temperature at which the data was written.
• The processing device determines the write temperature based on the first data.
• A read voltage value is calculated based on the write temperature.
• The processing device performs a second read operation on the memory device using the read voltage value to obtain the original data.

Potential Applications

• This technology can be applied in various memory devices such as solid-state drives (SSDs) and random-access memory (RAM).
• It can improve the read performance of memory devices by optimizing the read voltage based on the temperature at which the data was written.

Problems Solved

• Memory devices can experience variations in performance based on temperature.
• By considering the write temperature during the read operation, this technology helps mitigate the impact of temperature on read performance.
• It allows for more accurate retrieval of data, especially in scenarios where temperature fluctuations are common.

Benefits

• Improved read performance of memory devices.
• Enhanced accuracy in retrieving data, reducing the risk of errors.
• Increased reliability and efficiency of memory devices.
• Better adaptability to temperature changes, ensuring consistent performance.

Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a first read operation on the memory device to retrieve first data; determining, from the first data, second data indicative of a write temperature associated with the first data, wherein the write temperature is indicative of a temperature measured during a write operation; determining a read voltage value based on the second data; and performing a second read operation on the memory device using the read voltage value to obtain the first data.

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES (17859468)

Main Inventor

Vamsi Pavan Rayaprolu

Brief explanation

The patent application describes a system and method for maintaining data integrity in a memory device. Here is a simplified explanation of the abstract:

• The system includes a memory device and a processing device.
• The processing device performs operations on a set of memory cells that are configured to store a certain number of bits per cell.
• A data integrity check is performed on the memory cells to determine the data integrity metric value.
• The data integrity metric value is compared to a threshold criterion to determine if it meets the required level of integrity.
• If the data integrity metric value fails to meet the threshold criterion, the data from the source set of memory cells is copied to a different set of memory cells that can store a different number of bits per cell.

Potential applications of this technology:

• Data storage devices such as solid-state drives (SSDs) and flash memory devices.
• Cloud storage systems.
• Database systems.

Problems solved by this technology:

• Ensures data integrity in memory devices by performing data integrity checks.
• Provides a mechanism to copy data to a different set of memory cells if the integrity check fails.

Benefits of this technology:

• Improves the reliability and integrity of stored data.
• Reduces the risk of data corruption and loss.
• Allows for efficient use of memory cells by utilizing different configurations based on data integrity requirements.

Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

MEMORY ADDRESS TRANSLATION FOR DATA PROTECTION AND RECOVERY (18204821)

Main Inventor

Daniele Balluchi

Brief explanation

The abstract of the patent application describes a method for translating host commands to access data stored in memory devices with chip kill capability. This involves locating the host data as well as the parity data that is striped with the host data. The address translation process includes logical operations to determine the location of the parity data.

• The patent application focuses on address translation of host commands for accessing data stored in memory devices with chip kill capability.
• The method involves locating both the host data and the parity data that is striped with the host data.
• Logical operations, such as arithmetic operations, are used for locating the parity data during the address translation process.

Potential Applications

• This technology can be applied in various memory devices with chip kill capability, such as solid-state drives (SSDs) and RAID systems.
• It can be used in data centers, servers, and other computing systems that rely on memory devices for data storage and retrieval.

Problems Solved

• The technology solves the problem of efficiently locating both the host data and the parity data in memory devices with chip kill capability.
• It addresses the challenge of performing address translation for accessing data stored in memory devices with striped parity data.

Benefits

• The method provides an efficient and reliable way to translate host commands for accessing data in memory devices.
• By locating both the host data and the parity data, it ensures the integrity and availability of the stored data.
• The use of logical operations in the address translation process simplifies the overall system design and implementation.

Abstract

Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.

WRITE COMMAND EXECUTION FOR DATA PROTECTION AND RECOVERY SCHEMES (17831433)

Main Inventor

Nicola Del Gatto

Brief explanation

The abstract of this patent application describes a method for improving the efficiency and speed of write commands in memory devices. Here are the key points:

• Data blocks of a write command can be written to memory devices independently, without being grouped together for error correction.
• Different write commands can be executed together and simultaneously, rather than separately at different times.
• This approach reduces the latencies associated with executing write commands.

Potential Applications

This technology can be applied in various fields that utilize memory devices, such as:

• Computer systems
• Data storage devices
• Mobile devices
• Internet of Things (IoT) devices

Problems Solved

The technology addresses the following problems:

• Latency issues associated with executing write commands in memory devices.
• Inefficiencies caused by grouping data blocks together for error correction operations.

Benefits

The benefits of this technology include:

• Improved efficiency and speed of write commands in memory devices.
• Reduced latencies, leading to faster data processing.
• Simultaneous execution of different write commands, enhancing overall system performance.

Abstract

One or more data blocks of a write command can be written to memory devices independently of other data blocks that are grouped together for an error correction operation with the data blocks. Further, data blocks of different write commands can be executed together and simultaneously rather than being executed separately at different times, which can reduce the latencies associated with executing the write commands.

MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE (17877779)

Main Inventor

Robert Mason

Brief explanation

The abstract describes a method, apparatus, and system for managing memory self-recovery to correct failures caused by soft-error rate events. Here is a simplified explanation of the abstract:

• The self-recovery manager detects a failure in a memory device.
• It retrieves a set of register values from the memory device.
• The set of register values is stored by the self-recovery manager.
• A reset command is issued to the memory device, which generates a re-initialized set of register values.
• The self-recovery manager compares the original set of register values with the re-initialized set.
• If there is a discrepancy, the self-recovery manager triggers a self-recovery attempt using the comparison.

Potential applications of this technology:

• Memory management in computer systems
• Error correction in electronic devices
• Data recovery in storage systems

Problems solved by this technology:

• Soft-error rate events causing memory failures
• Loss of data or functionality due to memory device failures

Benefits of this technology:

• Automatic detection and recovery from memory failures
• Preservation of register values during the recovery process
• Improved reliability and stability of memory devices

Abstract

Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

CONTROLLING VARIATION OF VALID DATA COUNTS IN GARBAGE COLLECTION SOURCE BLOCKS (17830047)

Main Inventor

Xiangyu Tang

Brief explanation

The abstract describes a method for identifying and selecting blocks of memory for garbage collection in a memory device. The method involves considering factors such as the valid data count and data temperature of each block, and comparing them according to specific criteria. The selected block is then used as the source for garbage collection.

• Blocks of a memory device are identified based on a valid data count constraint.
• The first block is selected based on its valid data count.
• The second block is selected based on its data temperature.
• The first and second blocks are compared using one or more comparison criteria.
• Either the first or second block is chosen as the garbage collection source block based on the comparison.
• Garbage collection is performed at the selected source block.

Potential Applications:

• Memory management in computer systems and devices.
• Optimization of garbage collection processes in memory devices.

Problems Solved:

• Efficient identification and selection of blocks for garbage collection.
• Improved memory management and performance.

Benefits:

• More efficient garbage collection process.
• Optimal utilization of memory resources.
• Enhanced performance and reliability of memory devices.

Abstract

A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

LBAT BULK UPDATE (17946960)

Main Inventor

Steven R. Narum

Brief explanation

The abstract of this patent application describes an apparatus and methods for updating multiple data entries written to a memory device. The update operation is performed on data entries with the same offset from an initial physical address, based on received signaling indicating the performance of the operation.

• The patent application involves an apparatus and methods for updating data entries in a memory device.
• The update operation is performed on multiple data entries with the same offset from an initial physical address.
• The update is triggered by signaling indicating the performance of the operation.
• The apparatus and methods aim to efficiently update a plurality of data entries in a memory device.

Potential Applications

This technology can have various potential applications, including:

• Data storage systems: It can be used in memory devices and storage systems to efficiently update multiple data entries.
• Database management: The technology can be applied in database systems to improve the performance of updating data entries.
• File systems: It can be utilized in file systems to enhance the efficiency of updating multiple files.

Problems Solved

The technology addresses the following problems:

• Updating multiple data entries: It provides a solution for efficiently updating a plurality of data entries in a memory device.
• Performance optimization: The apparatus and methods aim to improve the performance of updating operations on data entries.
• Address offset management: By focusing on data entries with the same offset, the technology simplifies the update process.

Benefits

The use of this technology offers several benefits, including:

• Improved efficiency: The apparatus and methods optimize the update process, resulting in faster and more efficient operations.
• Enhanced performance: By focusing on data entries with the same offset, the technology can significantly improve the performance of updating operations.
• Simplified management: The approach of updating data entries with the same offset simplifies the overall management of the update process.

Abstract

Apparatus and methods include receiving signaling indicative of performance of an operation to update a plurality of data entries written to a memory device and having a same offset from an initial physical address corresponding to each of the plurality of data entries and performing the operation to write the update to the plurality of data entries written to the memory device and having the same offset from the initial physical address corresponding to each of the plurality of data entries responsive to receiving the signaling indicative of performance of the operation to update the plurality of data entries.

ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE (17842278)

Main Inventor

Li-Te Chang

Brief explanation

Explanation of the Abstract:

A processing device receives a read command for a specific logical address in a memory device. The processing device translates this logical address into a physical address, which specifies a wordline and a memory device die. If the physical block associated with the physical address is partially programmed, the processing device identifies a threshold voltage offset for the wordline. It then computes a modified threshold voltage by applying this offset to a read level associated with the memory device die. Finally, the processing device reads the data from the physical block using the modified threshold voltage.

• The patent application describes a method for reading data from a memory device using a modified threshold voltage.
• The processing device translates a logical address into a physical address, specifying a wordline and a memory device die.
• If the physical block is partially programmed, a threshold voltage offset associated with the wordline is identified.
• A modified threshold voltage is computed by applying the threshold voltage offset to a read level associated with the memory device die.
• The data from the physical block is then read using the modified threshold voltage.

Potential Applications:

• This technology can be applied in various memory devices, such as flash memory or non-volatile memory, to improve read operations.
• It can be used in electronic devices like smartphones, tablets, and computers to enhance memory performance and efficiency.
• The method can be implemented in data centers and servers to optimize data retrieval from memory devices.

Problems Solved by this Technology:

• Partially programmed physical blocks in memory devices can cause read errors or inefficiencies.
• Traditional read methods may not account for variations in threshold voltage, leading to inaccurate data retrieval.
• This technology addresses these issues by identifying threshold voltage offsets and computing a modified threshold voltage for more reliable and accurate data reading.

Benefits of this Technology:

• Improved read accuracy and efficiency by considering threshold voltage offsets.
• Enhanced performance of memory devices by optimizing data retrieval.
• Reduced read errors and improved reliability in partially programmed physical blocks.
• Increased overall efficiency and speed of electronic devices utilizing this technology.

Abstract

A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.

ROW HAMMER MITIGATION USING A VICTIM CACHE (17945702)

Main Inventor

Ameen D. Akel

Brief explanation

==Abstract==

Row hammer attacks exploit the unintended consequences of memory devices, where memory cells interact electrically and can leak charges, potentially altering the contents of neighboring memory rows. To mitigate such attacks, a victim cache is utilized. Data is written to cache lines of a cache, and the least recently used cache line is then written to the victim cache.

Patent/Innovation Explanation

• Row hammer attacks take advantage of memory devices' electrical interactions between memory cells.
• Memory cells can leak charges and modify nearby memory rows that were not originally accessed.
• The patent proposes the use of a victim cache to counter row hammer attacks.
• Data is written to cache lines in a cache.
• The least recently used cache line in the cache is written to the victim cache.

Potential Applications

• Enhancing the security of memory devices against row hammer attacks.
• Protecting sensitive data stored in memory from unauthorized access or modification.
• Improving the reliability and integrity of memory systems in various computing devices.

Problems Solved

• Mitigates the risk of row hammer attacks that can compromise the security and integrity of memory systems.
• Addresses the unintended side effects of memory devices, such as charge leakage and unintended modification of neighboring memory rows.
• Provides a solution to protect against unauthorized access or modification of data stored in memory.

Benefits

• Enhances the security and reliability of memory systems.
• Reduces the vulnerability to row hammer attacks.
• Safeguards sensitive data stored in memory from unauthorized access or modification.

Abstract

Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.

NAND PAGE BUFFER BASED SECURITY OPERATIONS (17814395)

Main Inventor

Jeremy BINFET

Brief explanation

The patent application describes a method for resolving a set of latches in a memory device to obtain initialized values. These initialized values are then used to generate a security key. 

• The memory device resolves a set of latches in a NAND page buffer to obtain initialized values.
• The initialized values are used to create a NAND page buffer initialized data set.
• A security key is generated using the NAND page buffer initialized data set.

Potential Applications

• This technology can be applied in various memory devices, such as solid-state drives (SSDs) and flash memory cards.
• It can enhance the security of data stored in these memory devices by generating unique security keys.

Problems Solved

• The method solves the problem of securely generating a security key for memory devices.
• It ensures that the security key is based on initialized values obtained from the NAND page buffer latches.

Benefits

• Improved security: The use of initialized values from the NAND page buffer latches enhances the security of the generated security key.
• Efficient data protection: The method provides an efficient way to generate unique security keys for memory devices, ensuring data protection.

Abstract

In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

CLASSIFICATION AND MITIGATION OF COMPUTE EXPRESS LINK SECURITY THREATS (17811770)

Main Inventor

Alessandro ORLANDO

Brief explanation

The patent application describes a system that enhances the security of a computing environment using compute express link (CXL) interface components. Here are the key points:

• The system includes servers that create virtual machines for computing.
• CXL interface components are used to communicate with the servers through CXL interconnects.
• A controller is configured to perform various security measures:

 * Encrypt protocol data to protect against security threats related to CXL interconnects or malicious extensions.
 * Verify the identity of the CXL interface components through a secure handshake process.
 * Establish a chain of trust rooted in the hardware of the CXL interface components.
 * Restrict access to a specific memory area that stores security data for verified or secured processes.
 * Conduct security checks and configure security features of the CXL interface components.

Potential applications of this technology:

• Cloud computing platforms that require secure communication between servers and virtual machines.
• Data centers that need to protect against security threats associated with CXL interconnects or malicious extensions.
• High-performance computing environments that require secure and trusted communication channels.

Problems solved by this technology:

• Mitigates security risks associated with CXL interposer security threats or malicious extensions.
• Ensures the authenticity and integrity of the CXL interface components.
• Protects sensitive security data stored in the memory of the CXL interface components.
• Establishes a secure and trusted computing environment.

Benefits of this technology:

• Enhanced security measures for computing environments using CXL interface components.
• Protection against potential security threats and unauthorized access.
• Secure communication channels between servers and virtual machines.
• Assurance of the authenticity and integrity of the CXL interface components.
• Ability to establish a chain of trust rooted in the hardware of the CXL interface components.

Abstract

In some implementations, a system includes a set of servers configured to establish a set of virtual machines to provide a computing environment; a set of compute express link (CXL) interface components configured to communicate with the set of servers via a set of CXL interconnects; and a controller configured to at least one of: encrypt protocol data against a CXL interposer security threat associated with the set of CXL interconnects or a malicious extension security threat, provide a secure handshake verification of an identity of the set of CXL interface components, enforce a chain of trust rooted in hardware of the set of CXL interface components; restrict access to an area of memory of the set of CXL interface components that stores security data for verified or secured processes; or perform a security check and set up a set of security features of the set of CXL interface components.

ESTABLISHING A CHAIN OF OWNERSHIP OF A DEVICE (17858560)

Main Inventor

Sourin SARKAR

Brief explanation

The abstract describes a method for establishing a chain of ownership for a device using blockchain technology. Here are the key points:

• The device determines ownership metadata based on ownership data associated with the device.
• The ownership metadata is split into two portions: one stored in the device's memory and the other transmitted to a server for storage in a blockchain ledger.
• By combining the ownership metadata stored in the device and the blockchain ledger, a chain of ownership for the device is established.

Potential Applications

• This technology can be applied to various industries where establishing a secure and verifiable chain of ownership is important, such as supply chain management, asset tracking, and intellectual property protection.

Problems Solved

• Establishing a reliable and tamper-proof chain of ownership has been a challenge in many industries. This technology solves this problem by utilizing blockchain technology to securely store ownership metadata.

Benefits

• The use of blockchain technology ensures the immutability and transparency of ownership records, reducing the risk of fraud and disputes.
• By decentralizing ownership records in a blockchain ledger, there is no single point of failure, enhancing the security and reliability of the chain of ownership.
• This method simplifies the process of establishing and verifying ownership, saving time and resources for businesses and individuals.

Abstract

Implementations described herein relate to establishing a chain of ownership of a device. In some implementations, the device may determine first ownership metadata based on first ownership data associated with the device. The device may split the first ownership metadata into a first portion of first ownership metadata and a second portion of first ownership metadata. The device may store, in the memory of the device, the first portion of first ownership metadata. The device may transmit, to a server, the second portion of first ownership metadata for storage in a blockchain ledger of a blockchain node. A chain of ownership associated with the device may be established based on a combination of the first portion of first ownership metadata stored in the memory of the device and the second portion of first ownership metadata stored in the blockchain ledger.

FIELD FIRMWARE UPDATE (17969916)

Main Inventor

Angelo Alberto Rovelli

Brief explanation

The abstract describes a patent application related to field firmware update (FFU) technology. The invention involves a memory module that receives an encrypted segment of a firmware (FW) package associated with FFU. The memory module then stores a decrypted segment of the FW package and re-encrypts it before communicating it to another memory module.

• The patent application relates to field firmware update (FFU) technology.
• A memory module receives an encrypted segment of a firmware (FW) package associated with FFU.
• The memory module stores a decrypted segment of the FW package.
• The memory module re-encrypts the decrypted segment of the FW package.
• The re-encrypted segment of the FW package is communicated to another memory module.

Potential Applications

• This technology can be applied in various electronic devices that require firmware updates, such as smartphones, tablets, computers, and IoT devices.
• It can be used in industrial equipment and machinery that rely on firmware for operation and require remote updates.
• The technology can be implemented in automotive systems to facilitate secure and efficient firmware updates for vehicle components.

Problems Solved

• The technology solves the problem of securely updating firmware in memory modules by encrypting and re-encrypting the FW package segments.
• It ensures that the FW package remains protected during the update process, preventing unauthorized access or tampering.
• The invention provides a reliable and efficient method for transferring FW package segments between memory modules.

Benefits

• The technology enables secure and efficient field firmware updates, reducing the risk of vulnerabilities and improving device performance.
• It allows for seamless updates without the need for physical access to the memory module, saving time and resources.
• The re-encryption process ensures the confidentiality and integrity of the FW package, enhancing overall system security.

Abstract

Methods, systems, and devices related to field firmware update (FFU). A first memory of a memory module may receive an encrypted segment of a FW package associated with FFU. A decrypted segment of the FW package may be stored by the first memory. A re-encrypted segment of the FW package may be stored by the first memory. The re-encrypted segment of the FW package may be communicated to a second memory of the memory module.

SECURING ELECTRONIC BALLOT SYSTEMS VIA SECURE MEMORY DEVICES WITH EMBEDDED HARDWARE SECURITY MODULES (17859892)

Main Inventor

Sourin Sarkar

Brief explanation

The abstract describes a method for electronic voting using an electronic voting machine (EVM). Here is a simplified explanation of the abstract:

• The EVM receives user data, including a unique code, from a user device.
• The EVM presents an interface for the user to cast their vote.
• Based on the user data and the vote, the EVM generates a command.
• The EVM verifies the validity of the command.
• The EVM encrypts the vote and user data for security.
• The encrypted vote is stored in a secure memory.

Potential Applications

• Electronic voting systems for elections, both in-person and remote.
• Secure voting systems for organizations, associations, and clubs.
• Online surveys and polls requiring secure and verifiable voting.

Problems Solved

• Ensures the integrity and security of electronic voting systems.
• Prevents tampering or manipulation of votes.
• Provides a verifiable and auditable record of votes.

Benefits

• Simplifies the voting process for users by using an electronic interface.
• Enhances the security and privacy of votes through encryption.
• Facilitates efficient and accurate counting of votes.
• Enables remote voting options, increasing accessibility and participation.

Abstract

In some aspects, the techniques described herein relate to a method including: receiving, by an electronic voting machine (EVM), user data from a user device, the user data including a unique code; presenting, by the EVM, an interface, the interface capable of receiving a vote; generating, by the EVM, a command based on the user data and the vote; determining, by the EVM, that the command is valid; encrypting, by the EVM, the vote and the user data; and writing, by the EVM, the vote to a secure memory.

SYSTEMS AND METHODS FOR EVALUATING AND SHARING HUMAN DRIVING STYLE INFORMATION WITH PROXIMATE VEHICLES (18448860)

Main Inventor

Robert Richard Noel Bielby

Brief explanation

The patent application describes systems and methods for analyzing and characterizing the driving style of a human driver. Here are the key points:

• The system includes sensors that collect information about driving characteristics while a human operates a vehicle.
• The collected data is evaluated using computer instructions stored in memory to identify patterns that correlate with the driver's style.
• The processor reads the instructions, analyzes the driving characteristics, and characterizes aspects of the driver's style based on the identified patterns.
• The patent also covers corresponding methods and non-transitory media for implementing this technology.

Potential applications of this technology:

• Driver monitoring systems in vehicles to provide feedback and coaching to improve driving skills.
• Insurance companies could use the data to assess risk and determine insurance premiums.
• Fleet management companies could use the technology to monitor and optimize driver performance.

Problems solved by this technology:

• Provides a quantitative and objective way to analyze and characterize a driver's style, which can be useful for various applications.
• Allows for personalized feedback and coaching to improve driving skills and safety.
• Enables better risk assessment and pricing for insurance companies.

Benefits of this technology:

• Improved safety on the roads by identifying and addressing risky driving behaviors.
• Potential cost savings for insurance companies and fleet management companies through better risk assessment and optimization.
• Enhanced driving experience for individuals through personalized feedback and coaching.

Abstract

Systems and methods for characterizing a driving style of a human driver are presented. A system may include one or more sensors configured to collect information concerning driving characteristics associated with operation of a vehicle by a human; a memory containing computer-readable instructions for evaluating the information concerning driving characteristics collected by the one or more sensors for one or more patterns correlatable with a driving style of the human and for characterizing aspects of the driving style of the human based on the one or more patterns; and a processor configured to read the computer-readable instructions from the memory, evaluate the driving characteristics collected by the one or more sensors for one or more patterns correlatable with a driving style of the human, and characterize aspects of the driving style of the human based on the one or more patterns. Corresponding methods and non-transitory media are disclosed.

TRACKING THE EFFECTS OF VOLTAGE AND TEMPERATURE ON A MEMORY DEVICE USING AN INTERNAL OSCILLATOR (17831114)

Main Inventor

Keun soo Song

Brief explanation

The abstract of this patent application describes a method for adjusting the propagation delay for write operations on a memory device based on the comparison of two oscillator counter values received at different times.

• A first oscillator counter value is received at a first time, and a second oscillator counter value is received at a second time.
• The first time occurs before the second time.
• The first oscillator counter value is compared to the second oscillator counter value.
• If the first and second oscillator counter values do not match, a propagation delay for write operations on a memory device is adjusted.

Potential applications of this technology:

• Memory devices in various electronic devices such as computers, smartphones, and tablets.
• Real-time systems that require precise synchronization and timing.

Problems solved by this technology:

• Inaccurate write operations on memory devices due to variations in oscillator counter values.
• Ensuring synchronization and timing accuracy in memory operations.

Benefits of this technology:

• Improved reliability and accuracy of write operations on memory devices.
• Enhanced synchronization and timing precision in real-time systems.

Abstract

A first oscillator counter value is received at a first time, and a second oscillator counter value is received at a second time. The first time precedes the second time. The first oscillator count value is compared to the second oscillator count value. responsive to determining that the first oscillator count value and the oscillator second count value do not match, a propagation delay for performing write operations on a memory device is adjusted.

ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE (17856691)

Main Inventor

Vamsi Pavan Rayaprolu

Brief explanation

The abstract describes a patent application that involves analyzing the performance of each die in a multi-die memory device and determining a temperature compensation value for each die based on the number of program erase cycles. This compensation value is then used to process memory access requests for each die. The patent application also includes a method to update the compensation equation based on a second analysis of each die.

• The patent application involves analyzing the performance of individual dies in a multi-die memory device.
• A temperature compensation value is determined for each die based on the number of program erase cycles.
• The compensation value is used to process memory access requests for each die.
• The patent application includes a method to update the compensation equation based on a second analysis of each die.

Potential Applications

• This technology can be applied in the field of memory devices, particularly multi-die memory devices.
• It can be used in various electronic devices that rely on memory storage, such as computers, smartphones, and tablets.

Problems Solved

• The technology addresses the issue of temperature variations affecting the performance of individual dies in a multi-die memory device.
• By determining temperature compensation values for each die, the technology ensures more accurate and reliable memory access processing.

Benefits

• The technology improves the overall performance and reliability of multi-die memory devices.
• It helps to mitigate the impact of temperature variations on memory access operations.
• By updating the compensation equation based on analysis, the technology can adapt to changing conditions and optimize memory access processing.

Abstract

A first analysis of each respective die of a multi-die memory device is performed. An equation to determine a respective temperature compensation (tempco) value for each respective die based on a number of program erase cycles (PECs) of the respective die based on the first analysis s determined. The equation for use in processing memory access requests directed to the respective die is stored. Whether to update the equation directed to the respective die based on a second analysis of the respective die is determined.

MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS (17805090)

Main Inventor

Jiyun Li

Brief explanation

The patent application describes multi-level cells and related methods, arrays, devices, and systems. It specifically focuses on a memory device that includes a memory array with different sections and digit lines. Here is a simplified explanation of the abstract:

• The memory device has a memory array with multiple sections.
• The first reference section has a certain number of memory cells and a reference digit line.
• The second reference section also has a certain number of memory cells and a reference digit line.
• The target section includes a memory cell and a first digit line connected to the memory cell through a first switch.
• The first digit line is also connected to the first reference digit line through a first sense amplifier.
• The target section also includes a second digit line connected to the first digit line through a second switch.
• The second digit line is further connected to the second reference digit line through a second sense amplifier.

Potential applications of this technology:

• Memory devices in various electronic devices such as smartphones, computers, and tablets.
• Data storage systems in cloud computing and data centers.
• Solid-state drives (SSDs) and other storage devices.

Problems solved by this technology:

• Increase in memory capacity and density by utilizing multi-level cells.
• Improved performance and reliability of memory devices.
• Efficient use of digit lines and sense amplifiers for data retrieval.

Benefits of this technology:

• Higher memory capacity and storage density in a compact device.
• Faster data retrieval and improved overall performance.
• Enhanced reliability and durability of memory devices.
• Cost-effective production and utilization of memory arrays.

Abstract

Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

PRE-DECODER CIRCUITY (17831290)

Main Inventor

Byung S. Moon

Brief explanation

The present disclosure is about pre-decoder circuitry in memory arrays. It describes a configuration where a positive voltage is applied to the first gate and a negative voltage is applied to the second gate of the decoder circuitry for a positive configuration of memory cells. For a negative configuration of memory cells, zero volts is applied to the first gate and a negative voltage is applied to the second gate.

• The patent application describes apparatuses, methods, and systems for pre-decoder circuitry in memory arrays.
• The pre-decoder circuitry includes a memory array with multiple memory cells.
• The decoder circuitry is connected to the memory array and consists of two n-type transistors with separate gates.
• The pre-decoder circuitry is designed to provide a bias condition for the gates of the transistors to generate a selection signal for one of the memory cells.
• The bias condition involves applying a positive voltage to the first gate and a negative voltage to the second gate for a positive configuration of memory cells.
• For a negative configuration of memory cells, the bias condition involves applying zero volts to the first gate and a negative voltage to the second gate.

Potential Applications

• Memory arrays in electronic devices
• Data storage systems
• Computer processors

Problems Solved

• Efficient selection of memory cells in a memory array
• Simplified circuitry design for memory decoding

Benefits

• Improved performance and reliability of memory arrays
• Reduced power consumption
• Simplified circuitry design

Abstract

The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

SYNCHRONOUS INPUT BUFFER ENABLE FOR DFE OPERATION (17831251)

Main Inventor

William C. Waldrop

Brief explanation

The patent application describes systems and methods for aligning a receiver enable signal with clocking signals to reduce the likelihood of false or incorrect data capture in a memory system. This alignment improves the operation of a decision feedback equalizer (DFE) by increasing the accuracy of distortion correction.

• Receiver enable signal alignment with clocking signals reduces the chances of false or incorrect data capture.
• Improved operation of a memory system is achieved by aligning receiver operations with clocking signals.
• The alignment enhances the accuracy of distortion correction performed by a decision feedback equalizer (DFE).

Potential Applications

This technology can be applied in various fields where memory systems are used, such as:

• Computer systems
• Mobile devices
• Data storage devices
• Networking equipment

Problems Solved

The technology addresses the following problems:

• False or incorrect data capture in memory systems
• Inaccurate distortion correction in decision feedback equalizers (DFEs)

Benefits

The use of this technology provides several benefits:

• Reduced likelihood of false or incorrect data capture
• Improved operation and performance of memory systems
• Increased accuracy of distortion correction in DFEs

Abstract

Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

MINIMUM MEMORY CLOCK ESTIMATION PROCEDURES (18201089)

Main Inventor

Erik V. Pohlmann

Brief explanation

The patent application describes methods, systems, and devices for estimating the minimum memory clock required for accessing memory cells. Here is a simplified explanation of the abstract:

• The device truncates a value of a first parameter associated with the duration of a clock cycle for a memory array.
• It determines a value of a second parameter that is inversely proportional to a combination of the truncated first parameter and a correction factor.
• The device then calculates the quantity of clock cycles required for accessing memory cells based on adjusting a third parameter associated with the second parameter.
• Finally, the device accesses the memory cells based on the determined quantity of clock cycles.

Potential Applications

This technology can have various applications in the field of memory systems and devices, including:

• Computer systems and servers
• Mobile devices and smartphones
• Embedded systems and IoT devices
• Gaming consoles and graphics processing units (GPUs)
• Data centers and cloud computing infrastructure

Problems Solved

The technology addresses the following problems in memory systems:

• Determining the minimum memory clock required for accessing memory cells accurately and efficiently.
• Accounting for variations and corrections in the clock cycle duration to optimize memory access.
• Ensuring reliable and timely access to memory cells for improved system performance.

Benefits

The use of this technology offers several benefits:

• Improved memory access efficiency and performance.
• Accurate estimation of the minimum memory clock required.
• Optimization of memory access based on the specific requirements of the memory array.
• Enhanced reliability and reduced latency in accessing memory cells.

Abstract

Methods, systems, and devices for minimum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may determine a value of a second parameter that is inversely proportional to a combination of the truncated first parameter and a correction factor. The device may determine a quantity of clock cycles associated with a second duration for accessing one or more memory cells of the memory array based on adjusting a third parameter associated with the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles.

TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES (18203877)

Main Inventor

Giorgio Servalli

Brief explanation

The abstract describes methods, systems, and devices for manufacturing ferroelectric memory devices using a self-aligned manufacturing technique. This technique involves forming a continuous layer of dielectric material over an assembly that includes an array of transistors and contacts. Cavities are then etched into the dielectric material, exposing the contacts. Bottom electrodes are formed on the sidewalls of each cavity by depositing and etching a layer of electrode material.

• A continuous layer of dielectric material is formed over an assembly containing transistors and contacts.
• Cavities are etched into the dielectric material, exposing the contacts.
• Bottom electrodes are formed on the sidewalls of each cavity by depositing and etching a layer of electrode material.

Potential Applications

• Manufacturing ferroelectric memory devices
• Memory arrays

Problems Solved

• Simplified and efficient manufacturing of ferroelectric memory devices
• Self-aligned manufacturing technique reduces the complexity of the manufacturing process

Benefits

• Improved manufacturing efficiency
• Enhanced memory device performance
• Cost-effective production

Abstract

Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

SWITCH AND HOLD BIASING FOR MEMORY CELL IMPRINT RECOVERY (17830100)

Main Inventor

Angelo Visconti

Brief explanation

The patent application describes methods, systems, and devices for recovering the imprint of memory cells. The imprint recovery procedure involves applying recovery pulses to memory cells with different voltage magnitudes. The first portion of each recovery pulse imposes a saturation polarization on the memory cell, while the second portion maintains the saturation polarization to prevent a reduction of polarization.

• The patent application focuses on switch and hold biasing for memory cell imprint recovery.
• The imprint recovery procedure includes applying recovery pulses to memory cells.
• Each recovery pulse has a first portion with a high voltage magnitude and a second portion with a lower voltage magnitude.
• The first voltage magnitude imposes a saturation polarization on the memory cell.
• The second voltage magnitude is high enough to maintain the saturation polarization of the memory cell.
• The recovery pulses are associated with a specific voltage polarity.
• The method prevents a reduction of polarization in the memory cell.

Potential Applications

This technology has potential applications in the following areas:

• Memory devices and systems
• Non-volatile memory technologies
• Ferroelectric capacitors

Problems Solved

The technology addresses the following problems:

• Imprint recovery in memory cells
• Reduction of polarization in memory cells
• Maintaining saturation polarization in memory cells

Benefits

The technology offers the following benefits:

• Improved recovery of imprint in memory cells
• Prevention of polarization reduction
• Enhanced performance and reliability of memory devices

Abstract

Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

ROBUST FUNCTIONALITY FOR MEMORY MANAGEMENT ASSOCIATED WITH HIGH-TEMPERATURE STORAGE AND OTHER CONDITIONS (17831368)

Main Inventor

Angelo Visconti

Brief explanation

The patent application describes methods, systems, and devices for memory management in high-temperature storage environments. Here is a simplified explanation of the abstract:

• A memory device applies a pattern to memory cells before or after a power state procedure.
• The pattern indicates a data state for each memory cell in a portion of memory cells.
• The pattern can be the same data state for each cell, alternating data states, or an asymmetric switching pattern over multiple cycles.
• The memory device writes logic values to memory cells based on the pattern.

Potential applications of this technology:

• High-temperature storage environments where memory devices need to function reliably.
• Industrial settings with extreme temperatures, such as manufacturing plants or oil refineries.
• Aerospace and automotive industries where memory devices are exposed to high temperatures.

Problems solved by this technology:

• Memory cells in high-temperature environments can experience data corruption or loss.
• Traditional memory management techniques may not be effective in extreme temperature conditions.
• The described methods provide a robust solution to maintain memory functionality in high-temperature storage.

Benefits of this technology:

• Improved reliability of memory devices in high-temperature environments.
• Enhanced data integrity and reduced risk of data loss or corruption.
• Increased lifespan of memory devices operating in extreme temperature conditions.

Abstract

Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.

TECHNIQUES FOR FLEXIBLE SELF-REFRESH OF MEMORY ARRAYS (18202149)

Main Inventor

Anthony D. Veches

Brief explanation

The patent application describes methods, systems, and devices for flexible self-refresh of memory arrays. Here are the key points:

• The memory system sets a refresh region for each memory bank by tracking access to memory row addresses in each bank.
• Access commands issued to each memory bank are monitored, and information is stored in a register of each bank.
• The memory system determines if a memory row address associated with an access command is within the refresh region and processes the respective memory bank accordingly.
• The memory bank's refresh region can be adjusted without affecting the refresh regions of other memory banks.

Potential Applications

This technology has potential applications in various fields, including:

• Computer systems
• Mobile devices
• Internet of Things (IoT) devices
• Embedded systems

Problems Solved

The technology addresses the following problems:

• Efficient self-refresh of memory arrays
• Flexibility in adjusting the refresh regions of memory banks
• Minimizing the impact on other memory banks during refresh operations

Benefits

The technology offers several benefits, including:

• Improved memory system performance
• Enhanced flexibility in managing memory refresh
• Reduced power consumption
• Increased reliability and lifespan of memory arrays

Abstract

Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

SIGNALING MEMORY ZONE RANKING INFORMATION (18204202)

Main Inventor

Giuseppe Cariello

Brief explanation

The abstract of this patent application describes methods, systems, and devices for signaling memory zone ranking information. Here is a simplified explanation:

• A first system determines ranking information for different zones of a memory.
• The ranking information is associated with a specific type of maintenance operation.
• The first system transmits the ranking information to a second system.
• The second system uses the ranking information to manage a different type of maintenance operation.

Potential Applications

This technology can have various applications in the field of memory management and maintenance. Some potential applications include:

• Data centers: This technology can be used in large-scale data centers to optimize memory maintenance operations and improve overall system performance.
• Cloud computing: Memory zone ranking information can be utilized in cloud computing environments to efficiently manage memory resources and enhance the performance of virtual machines.
• Embedded systems: This innovation can be applied in embedded systems to prioritize memory maintenance tasks and ensure optimal operation of the system.

Problems Solved

The technology described in this patent application addresses several problems related to memory management and maintenance. These problems include:

• Inefficient memory maintenance: Without proper ranking information, memory maintenance operations can be performed in a suboptimal manner, leading to decreased system performance.
• Resource wastage: In the absence of ranking information, memory resources may be allocated inefficiently, resulting in unnecessary resource consumption.
• Lack of coordination: Without signaling ranking information between systems, there can be a lack of coordination in managing different types of maintenance operations, leading to potential conflicts and inefficiencies.

Benefits

The utilization of this technology offers several benefits in memory management and maintenance. These benefits include:

• Improved performance: By using ranking information, memory maintenance operations can be prioritized and optimized, leading to enhanced system performance.
• Efficient resource allocation: The ranking information enables better allocation of memory resources, reducing wastage and improving resource utilization.
• Enhanced coordination: Signaling ranking information between systems allows for better coordination in managing different types of maintenance operations, minimizing conflicts and improving overall efficiency.

Abstract

Methods, systems, and devices for signaling memory zone ranking information are described. A first system may determine ranking information for zones of a memory. The ranking information may be associated with a first type of maintenance operation. The first system may transmit the ranking information to a second system. The second system may use the ranking information to manage a second type of maintenance operation.

DYNAMIC ROW HAMMERING THRESHOLD FOR MEMORY (17809144)

Main Inventor

Sujeet V. Ayyapureddi

Brief explanation

Methods, systems, and devices for a dynamic row hammering threshold for memory are described in this patent application. The memory device implements a dynamic threshold for a set of multiple rows of the memory device, which helps decrease the likelihood of a large quantity of refresh operations for rows that are close to being hammered occurring within a short time span.

• The memory device determines the quantity of rows that exceed a row hammering threshold during a refresh duration.
• The memory device also determines the total quantity of activate operations performed across the set of rows during the refresh duration.
• Based on these determinations, the memory device alters the dynamic threshold.
• The dynamic threshold can be altered based on the quantity of rows, the quantity of activate operations, or both.

Potential Applications

• This technology can be applied in various memory devices, such as RAM (Random Access Memory) modules, to prevent row hammering and improve overall performance and reliability.

Problems Solved

• Row hammering is a phenomenon where repeated activation of certain rows in a memory device can cause bit flips in nearby rows, leading to data corruption and system instability.
• By implementing a dynamic threshold, this technology helps mitigate the risk of row hammering and reduces the occurrence of refresh operations for rows that are close to being hammered.

Benefits

• Improved memory device performance and reliability by reducing the likelihood of row hammering.
• Enhanced data integrity and system stability by preventing bit flips caused by row hammering.
• Optimal utilization of memory resources by dynamically adjusting the threshold based on the actual quantity of rows and activate operations.

Abstract

Methods, systems, and devices for a dynamic row hammering threshold for memory are described. A memory device may implement a dynamic threshold, such as a threshold quantity of activate operations or a row hammering threshold, for a set of multiple rows of the memory device. For example, the memory device may determine a quantity of rows which exceed a row hammering threshold during a refresh duration and a total quantity of activate operations performed across the set of rows during the refresh duration, and may alter the dynamic threshold based on the quantity of rows, the quantity of activate operations, or both. By altering the dynamic threshold, the memory device may decrease a likelihood that a relatively large quantity of refresh operations for rows that are close to being hammered occur within a short time span.

ROW HAMMER REFRESH OPERATION (17959664)

Main Inventor

John Christopher M. Sancon

Brief explanation

The abstract describes a patent application related to a row hammer refresh operation in memory devices. The invention involves an apparatus with an array of memory cells, including multiple dies, one of which is a row hammer die. The apparatus also includes a memory controller that performs various operations on the memory cells. The memory controller detects the number of accesses associated with the row hammer die and, based on the number of operations performed, performs a refresh operation on a group of memory cells in another die when a threshold quantity of accesses is reached.

• An apparatus for managing memory cells in a memory device is described in the patent application.
• The apparatus includes an array of memory cells, with multiple dies, one of which is a row hammer die.
• A memory controller is coupled to the array of memory cells and performs operations on them.
• The memory controller detects the number of accesses associated with the row hammer die.
• When a threshold quantity of accesses is reached, the memory controller performs a refresh operation on a group of memory cells in another die.

Potential Applications

• This technology can be applied in various memory devices, such as computer RAM or solid-state drives.
• It can help prevent data corruption and improve the reliability of memory systems.

Problems Solved

• Row hammer is a phenomenon where repeated accesses to a specific row of memory cells can cause bit flips in neighboring rows.
• This technology solves the problem of row hammer by detecting the number of accesses and performing refresh operations to prevent data corruption.

Benefits

• By performing refresh operations on specific groups of memory cells, this technology mitigates the effects of row hammer and improves the overall reliability of memory systems.
• It helps to extend the lifespan of memory devices by preventing data corruption and reducing the occurrence of bit flips.

Abstract

Systems, apparatuses, and methods related to a row hammer refresh operation are described herein. An example apparatus can include an array of memory cells of a memory device. The array of memory cells can include a plurality of dies and at least one of the plurality of dies is a row hammer die. The example apparatus can include a memory controller coupled to the array of memory cells. The memory controller can perform a number of operations on the array of memory cells. The memory controller can detect a quantity of accesses associated with the row hammer die and based on the number of operations performed. The memory controller can, in response to detection of a threshold quantity of accesses of a group of memory cells in the row hammer die, perform a refresh operation on a group of memory cells in an additional die of the plurality of dies.

TECHNIQUES FOR MEMORY CELL RESET USING DUMMY WORD LINES (18310715)

Main Inventor

Yuan He

Brief explanation

The patent application describes methods, systems, and devices for resetting memory cells using dummy word lines. Here is a simplified explanation of the abstract:

• The memory device uses dummy word lines to connect a voltage node with a bit line during a reset operation.
• This allows the bit line to be supplied with a reset voltage from the voltage node.
• The memory device then activates word lines to connect the bit line with memory cells, supplying them with the reset voltage to reset them.
• During the reset operation, certain components of a sense amplifier coupled with the bit line may be disabled to support the voltage node supplying the reset voltage.

Potential applications of this technology:

• Memory devices, such as flash memory or DRAM, can benefit from this technique for resetting memory cells.
• It can be used in various electronic devices that rely on memory, such as smartphones, tablets, computers, and IoT devices.

Problems solved by this technology:

• Resetting memory cells is a crucial operation in memory devices, and this technique provides an efficient and reliable way to achieve it.
• By using dummy word lines and disabling certain components, the voltage node can supply the reset voltage to the bit line without interference, ensuring proper resetting of memory cells.

Benefits of this technology:

• Improved reliability and efficiency in resetting memory cells.
• Reduces the chances of errors or inconsistencies during the reset operation.
• Enables faster and more accurate data storage and retrieval in memory devices.

Abstract

Methods, systems, and devices for techniques for memory cell reset using dummy word lines are described. A memory device may activate, as part of a reset operation, one or more dummy word lines to couple a voltage node with a bit line to supply the bit line with a reset voltage supplied to the voltage node. The memory device may then activate one or more word lines to couple the bit line with one or more memory cells to supply the one or more memory cells with the reset voltage such that the one or more memory cells are reset. In some cases, the memory device may disable one or more components of a sense amplifier coupled with the bit line during the reset operation to support the voltage node supplying the bit line with the reset voltage.

TIMING ADJUSTMENT FOR DATA INPUT/OUTPUT BUFFER CIRCUITS (17834754)

Main Inventor

NORIAKI MOCHIDA

Brief explanation

The patent application describes apparatuses with a loopback circuit that includes a signal multiplexer and a selector. The loopback circuit is connected to multiple input signal receivers.

• The loopback circuit takes an input signal received at one of the input receivers and provides it as a selected signal.
• The selector, connected to the signal multiplexer, generates a loopback signal based on the selected signal and an alleviation signal that periodically transitions between two different states.

Potential Applications

• Testing and debugging electronic devices and systems.
• Signal integrity analysis in communication networks.
• Verifying the functionality of input signal receivers.

Problems Solved

• Provides a way to test and verify the functionality of input signal receivers without the need for external equipment.
• Allows for efficient signal integrity analysis in communication networks.
• Simplifies the testing and debugging process of electronic devices and systems.

Benefits

• Simplifies the testing process by eliminating the need for external equipment.
• Provides a cost-effective solution for signal integrity analysis.
• Increases efficiency in testing and debugging electronic devices and systems.

Abstract

Apparatuses including a loopback circuit are disclosed. An example apparatus according to the disclosure includes a plurality of input signal receivers and a loopback circuit coupled to the plurality of input signal receivers. The loopback circuit includes a signal multiplexer and a selector. The signal multiplexer provides an input signal received at one input receiver of the plurality of input receivers as a selected signal. The selector coupled to the signal multiplexer provides a loopback signal based on the selected signal and an alleviation signal that transitions between two different states, periodically.

MAXIMUM MEMORY CLOCK ESTIMATION PROCEDURES (17929970)

Main Inventor

Erik V. Pohlmann

Brief explanation

The patent application describes methods, systems, and devices for estimating the maximum memory clock speed. Here is a simplified explanation of the abstract:

• The device truncates a value of a first parameter associated with the duration of a clock cycle for a memory array.
• It then estimates a value of a second parameter that is inversely proportional to the truncated value of the first parameter.
• The device determines the number of clock cycles required to access the memory cells of the memory array based on the adjusted second parameter.
• Finally, the device accesses the memory cells of the memory array using the determined number of clock cycles.

Potential applications of this technology:

• This technology can be used in host devices to optimize the memory clock speed for efficient memory access.
• It can be implemented in various electronic devices that use memory arrays, such as computers, smartphones, and gaming consoles.

Problems solved by this technology:

• The technology solves the problem of determining the maximum memory clock speed for accessing memory cells without causing errors or inefficiencies.
• It provides a method to estimate the number of clock cycles required for accessing memory cells based on the duration of the clock cycle.

Benefits of this technology:

• By estimating the maximum memory clock speed, this technology allows for efficient memory access, improving overall system performance.
• It helps in avoiding errors and inefficiencies that can occur when accessing memory cells at a clock speed that exceeds the maximum limit.

Abstract

Methods, systems, and devices for maximum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may estimate a value of a second parameter that is inversely proportional to the truncated value of the first parameter. The device may determine a quantity of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based on adjusting the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles associated with the maximum duration.

ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS (18204786)

Main Inventor

Edmund J. Gieske

Brief explanation

The abstract describes an apparatus that includes memory devices and a controller. The controller has row hammer detection circuitry that receives signaling for a row activation command with a row address. It increments a row counter corresponding to the row address stored in a data structure and determines if the incremented row counter exceeds a row hammer threshold. If it does, the controller issues a row hammer mitigation command to mitigate row hammer.

• The apparatus includes memory devices and a controller.
• The controller has row hammer detection circuitry.
• The row hammer detection circuitry receives signaling for a row activation command with a row address.
• The row counter corresponding to the row address is incremented and stored in a data structure.
• The incremented row counter is compared to a row hammer threshold.
• If the incremented row counter exceeds the threshold, a row hammer mitigation command is issued.

Potential Applications

• This technology can be applied in computer systems that use memory devices.
• It can be used in servers, data centers, and other computing environments where memory performance and reliability are crucial.

Problems Solved

• Row hammer is a phenomenon where repeated accesses to a row of memory cells can cause bit flips in adjacent rows, leading to data corruption and system instability.
• This technology solves the problem of row hammer by detecting and mitigating the effects of repeated row activations.

Benefits

• By detecting and mitigating row hammer, this technology improves the reliability and stability of memory systems.
• It helps prevent data corruption and system crashes caused by row hammer.
• The mitigation commands issued by the controller can help extend the lifespan of memory devices by reducing the wear and tear caused by row hammer.

Abstract

An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.

DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES (17830042)

Main Inventor

Lorenzo Fratin

Brief explanation

The abstract describes a patent application for decoder architectures for three-dimensional memory devices. The decoder includes two portions - a first portion manufactured on top of the memory array and a second portion implemented in a separate semiconductor device. The first portion includes a pillar decoding portion and a word line decoding portion, while the second portion includes logic circuits to drive signals to contacts of the first portion.

• The decoder architecture is designed for three-dimensional memory devices.
• It includes two portions - one on top of the memory array and another in a separate semiconductor device.
• The first portion includes a pillar decoding portion and a word line decoding portion.
• The second portion includes logic circuits to drive signals to contacts of the first portion.

Potential Applications

• Three-dimensional memory devices
• Semiconductor devices

Problems Solved

• Efficient decoding of memory arrays in three-dimensional memory devices
• Integration of separate semiconductor devices with memory arrays

Benefits

• Improved performance and efficiency in three-dimensional memory devices
• Simplified integration of separate semiconductor devices with memory arrays

Abstract

Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.

PRE-DECODER CIRCUITY (17831332)

Main Inventor

Jin Seung Son

Brief explanation

The patent application describes a technology for pre-decoder circuitry used in memory arrays. The circuitry includes a decoder and pre-decoder circuitry that provide bias conditions to select memory cells. 

• The pre-decoder circuitry includes two types of transistors and provides different voltages to the gates of these transistors based on the memory cell configuration.
• For a positive memory cell configuration, the first gate receives a positive voltage and the second gate receives a negative voltage.
• For a negative memory cell configuration, the first gate receives zero volts and the second gate receives a negative voltage.
• The pre-decoder circuitry consists of two parts: first pre-decoder circuitry that provides the positive voltage and zero volts, and second pre-decoder circuitry that provides the negative voltage.

Potential applications of this technology:

• Memory arrays in electronic devices such as computers, smartphones, and tablets.
• Data storage systems in servers and data centers.
• High-performance computing systems that require efficient memory access.

Problems solved by this technology:

• Efficient selection of memory cells in a memory array.
• Simplification of the pre-decoder circuitry design.
• Improved performance and reliability of memory arrays.

Benefits of this technology:

• Faster and more accurate selection of memory cells.
• Reduced power consumption in memory arrays.
• Improved overall performance and efficiency of electronic devices.

Abstract

The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.

Pre-Sense Gut Node Amplification in Sense Amplifier (17829737)

Main Inventor

Huy T. Vo

Brief explanation

The patent application describes a memory device that includes multiple memory cells and digit lines for data storage and transfer. The device also includes multiple sense amplifiers that are selectively connected to the digit lines. 

• The sense amplifiers perform threshold compensation for NMOS transistors by storing voltages proportional to their respective threshold voltages.
• The sense amplifiers amplify the differential voltage between the two nodes by charging one node and discharging the other node based on the charges of the digit lines.

Potential Applications

• Memory devices in computer systems
• Solid-state drives (SSDs)
• Mobile devices such as smartphones and tablets

Problems Solved

• Threshold compensation helps in maintaining accurate data storage and retrieval in memory cells.
• Amplification of differential voltage improves the signal-to-noise ratio and enhances data transfer efficiency.

Benefits

• Improved reliability and accuracy of data storage and retrieval in memory devices.
• Enhanced performance and efficiency of memory devices.
• Higher signal-to-noise ratio for better data transfer quality.

Abstract

A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

Sense Amplifier Reference Voltage Through Sense Amplifier Latch Devices (17860470)

Main Inventor

Eric Carman

Brief explanation

The abstract describes a patent application for sense amplifiers used in memory devices. These sense amplifiers include latch transistors that latch values based on charges in memory cells. 

• The sense amplifier uses a first latch transistor to apply a reference voltage to a first gut node of the sense amplifier.
• The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier.
• The sense amplifier latches a value based on the relationship between the reference voltage and the charge.

Potential Applications

• Memory devices
• Computer systems
• Electronic devices

Problems Solved

• Efficiently latching values based on charges in memory cells
• Improving the performance of sense amplifiers in memory devices

Benefits

• Enhanced memory device performance
• Improved reliability and accuracy in reading memory cell charges
• Increased efficiency in memory operations

Abstract

Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.

TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS (17864046)

Main Inventor

Ferdinando Bedeschi

Brief explanation

The patent application describes a memory device that uses storage class memory, such as flash memory.

• The memory device has a memory array consisting of memory cells arranged as differential memory cell pairs.
• Each memory cell pair stores a single logical bit.
• The memory device is controlled by a controller that receives commands from a host to perform read operations.
• The memory cell pair is selected using bitlines and a common wordline.
• A partition of the memory array is accessed to read the data stored by the memory cell pair.
• The read data is then stored in a latch for sending to the host.
• A counter is incremented in response to accessing the partition.
• The controller uses statistical analysis to determine whether to perform a refresh operation for the partition.
• The determination is based on comparing the current value of the counter to a value previously generated by a random number generator.

Potential Applications

• This technology can be applied in various memory devices, such as solid-state drives (SSDs) and other storage devices.
• It can be used in computer systems, servers, and other electronic devices that require high-performance memory.

Problems Solved

• The technology solves the problem of efficiently reading data from memory cells in a memory device.
• It addresses the issue of determining when to perform a refresh operation for memory partitions to maintain data integrity.

Benefits

• The memory device allows for efficient read operations by accessing specific memory cell pairs and storing the read data in a latch.
• The statistical analysis performed by the controller helps optimize the refresh operation, reducing unnecessary refresh cycles.
• By using a random number generator, the refresh operation can be performed in a more balanced and controlled manner, improving overall memory performance and reliability.

Abstract

Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.

MEMORY ARRAY SEASONING (18196268)

Main Inventor

Andrea Martinelli

Brief explanation

The abstract describes methods, systems, and devices for memory array seasoning. This involves performing a seasoning operation on memory cells with high threshold voltage. The operation includes activating a bit line and a word line associated with the target memory cell. Additionally, a word line connected to a helper memory cell that shares the activated bit line may also be activated. This increases the current flowing across the target memory cell, reducing its threshold voltage.

• Memory array seasoning methods, systems, and devices are described in a patent application.
• The seasoning operation is performed on memory cells with high threshold voltage.
• The target memory cell is seasoned by activating its associated bit line and word line.
• A word line connected to a helper memory cell sharing the activated bit line may also be activated.
• Increasing the current flowing across the target memory cell helps reduce its threshold voltage.

Potential Applications

This technology can be applied in various fields, including:

• Memory manufacturing industry
• Semiconductor industry
• Electronics industry

Problems Solved

The technology addresses the following problems:

• Memory cells with high threshold voltage
• Inefficient memory cell performance
• Inconsistent memory cell behavior

Benefits

The technology offers the following benefits:

• Improved memory cell performance
• Enhanced consistency in memory cell behavior
• Increased efficiency in memory operations

Abstract

Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.

PRE-DECODER CIRCUITRY (17831311)

Main Inventor

Vijayakrishna J. Vankayala

Brief explanation

The present disclosure describes a technology called pre-decoder circuitry, which is used in memory arrays to select specific memory cells for operation. The pre-decoder circuitry includes a combination of transistors and bias conditions to provide selection signals to the memory cells.

• The pre-decoder circuitry includes a memory array with multiple memory cells.
• The decoder circuitry is connected to the memory array and consists of a p-type transistor, a first n-type transistor, and a second n-type transistor.
• The pre-decoder circuitry is designed to provide a bias condition to the gates of the transistors, which determines the selection signal for the memory cells.
• In a positive configuration, the bias condition sets the first gate, second gate, and third gate to zero volts, providing a selection signal to a specific memory cell.
• In a negative configuration, the bias condition sets the third gate to a negative voltage and the first gate and second gate to zero volts, providing a selection signal to a different memory cell.

Potential applications of this technology:

• Memory arrays in electronic devices such as computers, smartphones, and tablets.
• Any application that requires efficient and accurate selection of specific memory cells.

Problems solved by this technology:

• Efficient selection of specific memory cells in a memory array.
• Accurate and reliable operation of memory cells.

Benefits of this technology:

• Improved performance and efficiency of memory arrays.
• Enhanced reliability and accuracy in memory cell selection.
• Simplified circuitry design for memory arrays.

Abstract

The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

INTERNAL REFERENCE RESISTOR FOR NON-VOLATILE MEMORY (17831414)

Main Inventor

Neil Petrie

Brief explanation

The abstract describes an example apparatus that includes an array of memory cells and a memory controller. The memory controller has an internal reference resistor and is configured to monitor memory characteristics for the array and the memory controller. It can also trim the internal reference resistor to achieve a target resistance value based on the memory characteristics.

• The apparatus includes an array of memory cells and a memory controller.
• The memory controller has an internal reference resistor.
• The memory controller monitors memory characteristics for the array and itself.
• The memory controller trims the internal reference resistor to achieve a target resistance value based on the memory characteristics.

Potential Applications

• This technology can be applied in various memory devices such as solid-state drives (SSDs), random-access memory (RAM), and non-volatile memory (NVM).
• It can be used in electronic devices like smartphones, tablets, computers, and IoT devices that rely on memory storage.

Problems Solved

• The technology solves the problem of maintaining accurate memory characteristics in memory devices.
• It addresses the challenge of ensuring consistent and reliable performance of memory cells over time.
• It solves the issue of maintaining the desired resistance value in the internal reference resistor.

Benefits

• The memory controller's ability to monitor and trim the internal reference resistor allows for precise control of memory characteristics.
• By adjusting the internal reference resistor, the memory controller can compensate for variations and aging effects, ensuring consistent performance.
• The technology improves the overall reliability and longevity of memory devices by actively managing memory characteristics.

Abstract

An example apparatus include an array of memory cells. The example apparatus includes a memory controller coupled to the array. The memory controller can include an internal reference resistor. The memory controller can be configured to monitor memory characteristics for the array and the memory controller. The memory controller can be configured to trim the internal reference resistor to result in a target resistance value based on the memory characteristics.

FORWARD-LOOKING DETERMINATION OF READ VOLTAGE USING MEMORY CELL PATTERNS (17855483)

Main Inventor

Umberto di Vincenzo

Brief explanation

The patent application describes a memory device that uses multiple groups of pattern cells to select a voltage for reading memory cells. 

• The memory device includes multiple groups of pattern cells.
• Different magnitude levels of voltages are applied to each group of pattern cells.
• The controller determines which group of pattern cells first switch at the lowest magnitude of applied voltage.
• Based on the first group to switch, the controller selects a read voltage.
• The selected read voltage is used to read data cells corresponding to a codeword.

Potential Applications

This technology has potential applications in various fields, including:

• Memory devices and systems
• Data storage and retrieval systems
• Computer hardware and electronics industry

Problems Solved

The technology addresses the following problems:

• Efficient selection of voltage for reading memory cells
• Improved reliability and accuracy in reading data cells
• Optimization of memory device performance

Benefits

The technology offers the following benefits:

• Enhanced speed and efficiency in reading memory cells
• Improved data retrieval and storage capabilities
• Increased reliability and accuracy in memory operations

Abstract

Systems, methods, and apparatus for a memory device that uses multiple groups of pattern cells to select a voltage for reading memory cells. In one approach, a controller applies different magnitude levels of voltages to each of the groups of pattern cells. The controller determines which of the groups have pattern cells that first switch (e.g., switch at the lowest magnitude of applied voltage). Based on identifying the first group to switch, the controller selects a read voltage. The selected read voltage is used to read data cells (e.g., corresponding to a codeword).

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17851865)

Main Inventor

Jordan D. Greenlee

Brief explanation

The abstract describes a method for forming a memory array using memory cells. Here are the key points:

• The memory array is formed by creating memory block regions, each consisting of a vertical stack of insulative and conductive tiers.
• Channel-material strings run through the insulative and conductive tiers.
• The conductive tiers have void spaces that extend laterally across the memory block regions.
• Either conductive or semiconductive material is formed in the void spaces, outside of the channel-material strings.
• A conductive molybdenum-containing metal material is then formed directly against the conductive or semiconductive material.
• A conductive line is formed from the conductive molybdenum-containing metal material.
• The conductive or semiconductive material has a different composition from the conductive molybdenum-containing metal material.

Potential applications of this technology:

• Memory arrays for electronic devices such as computers, smartphones, and tablets.
• Data storage systems for servers and data centers.
• Embedded memory in integrated circuits for various electronic devices.

Problems solved by this technology:

• Provides a method for forming memory arrays with improved performance and reliability.
• Allows for the efficient use of space within the memory block regions.
• Enables the creation of memory cells with different compositions for enhanced functionality.

Benefits of this technology:

• Improved memory array performance and reliability.
• Increased data storage capacity.
• Enhanced functionality and versatility in memory cell design.

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18327846)

Main Inventor

Rui Zhang

Brief explanation

The patent application describes a microelectronic device that consists of a stack structure with blocks separated by dielectric slot structures. Each block contains a vertically alternating sequence of conductive and insulative structures arranged in tiers. The blocks also have a stadium structure with opposing staircase structures, where the steps are made up of the edges of the tiers. Additionally, the blocks include a filled trench that is located vertically above and within the horizontal boundaries of the stadium structure. The filled trench consists of dielectric liner structures and additional dielectric liner structures with a different material composition, alternating with each other. The filled trench also contains dielectric fill material that covers an alternating sequence of the dielectric liner structures and additional dielectric liner structures.

• Microelectronic device with a stack structure and blocks separated by dielectric slot structures
• Blocks have a stadium structure with opposing staircase structures made of edges of tiers
• Filled trench located vertically above and within the horizontal boundaries of the stadium structure
• Filled trench includes alternating dielectric liner structures and additional dielectric liner structures with different material composition
• Dielectric fill material covers alternating sequence of dielectric liner structures and additional dielectric liner structures

Potential Applications

• Integrated circuits
• Microprocessors
• Memory devices
• Semiconductor devices

Problems Solved

• Improved performance and functionality of microelectronic devices
• Enhanced electrical conductivity and insulation properties
• Efficient use of space within the device

Benefits

• Higher efficiency and speed in microelectronic devices
• Increased storage capacity
• Improved reliability and durability of the device

Abstract

A microelectronic device includes a stack structure including blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The blocks including a stadium structure including opposing staircase structures each having steps comprising edges of the tiers. The blocks further include a filled trench vertically overlying and within horizontal boundaries of the stadium structure. The filled trench includes dielectric liner structures and additional dielectric liner structures having a different material composition than that of the dielectric liner structures and alternating with the dielectric liner structures. The filled trench also includes dielectric fill material overlying an alternating sequence of the dielectric liner structures and additional dielectric liner structures.

INTERLEAVED STRING DRIVERS, STRING DRIVER WITH NARROW ACTIVE REGION, AND GATED LDD STRING DRIVER (18237070)

Main Inventor

Michael A. Smith

Brief explanation

The patent application describes a memory device that includes two string driver circuits arranged next to each other. These circuits are arranged in an interleaved layout configuration, where the connections of the first string driver are offset from the connections of the second string driver. This arrangement allows for a shorter pitch length between the connections compared to a non-interleaved layout configuration.

• The memory device includes two string driver circuits arranged next to each other.
• The first and second string driver circuits are arranged in an interleaved layout configuration.
• The connections of the first string driver are offset from the connections of the second string driver.
• The interleaved layout configuration allows for a shorter pitch length between the connections.
• The shorter pitch length is achieved by reducing the effective distance between the corresponding opposing connections.

Potential applications of this technology:

• Memory subsystems in electronic devices such as computers, smartphones, and tablets.
• Solid-state drives (SSDs) and other storage devices that require efficient memory management.

Problems solved by this technology:

• The interleaved layout configuration reduces the pitch length between connections, allowing for more efficient memory management.
• The offset arrangement of the connections enables a shorter effective distance between opposing connections, improving the overall performance of the memory device.

Benefits of this technology:

• Improved memory management efficiency due to the shorter pitch length between connections.
• Enhanced performance of the memory device through the interleaved layout configuration.
• Increased data transfer speeds and reduced latency in memory subsystems.

Abstract

A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

MEMORY CELL VOLTAGE LEVEL SELECTION (17876346)

Main Inventor

Tingjun Xie

Brief explanation

The abstract of the patent application describes a method for managing write and read operations in a quad-level cell (QLC) memory block. Here is a simplified explanation:

• The method involves performing a certain number of write operations on a QLC memory block over a specific time period.
• If the time period exceeds a predetermined threshold, the QLC memory block is designated as a bimodal.
• The method then determines the voltage threshold level of the last successful read operation associated with the QLC memory block.
• Finally, the read threshold level of at least a portion of the QLC memory block is set to the voltage threshold level of the last successful read operation.

Potential Applications:

• This technology can be applied in the field of data storage, particularly in QLC memory blocks used in solid-state drives (SSDs) or other storage devices.
• It can improve the reliability and performance of QLC memory blocks by dynamically adjusting the read threshold level based on the voltage threshold level of successful read operations.

Problems Solved:

• QLC memory blocks can experience degradation and errors over time due to repeated write operations.
• By designating the QLC memory block as a bimodal and adjusting the read threshold level, this method helps mitigate the impact of degradation and errors, improving the overall reliability of the memory block.

Benefits:

• Improved reliability: By setting the read threshold level based on successful read operations, the method ensures accurate data retrieval even in the presence of degradation or errors.
• Enhanced performance: The dynamic adjustment of the read threshold level optimizes the read operations, leading to improved performance of the QLC memory block.
• Extended lifespan: By managing the write and read operations, the method helps prolong the lifespan of the QLC memory block, reducing the need for frequent replacements.

Abstract

A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

WRITE-ONCE MEMORY ENCODED DATA (17944692)

Main Inventor

Xiangyu Tang

Brief explanation

The patent application describes a method for encoding and storing data in flash memory cells. Here is a simplified explanation of the abstract:

• The method starts by receiving initial data.
• It then determines the number of programming operations performed on a group of flash memory cells since the last erase operation.
• The initial data is encoded to create a write-once memory (WOM) encoded data.
• Finally, the WOM encoded data is stored in a specific number of flash memory cells, taking into account the determined number of programming operations.

Potential applications of this technology:

• Data storage in flash memory devices such as solid-state drives (SSDs) and USB flash drives.
• Secure data storage where the encoded data cannot be modified or tampered with.

Problems solved by this technology:

• Data integrity: By using write-once memory encoding, the method ensures that the stored data remains unchanged and cannot be modified.
• Efficient use of flash memory: By considering the number of programming operations, the method optimizes the storage of data in flash memory cells, reducing wear and extending the lifespan of the memory.

Benefits of this technology:

• Data security: The write-once memory encoding provides a level of data security by preventing unauthorized modifications.
• Extended flash memory lifespan: By optimizing the storage of data based on programming operations, the method helps prolong the lifespan of flash memory cells.
• Efficient use of storage space: The method ensures efficient utilization of flash memory cells, maximizing the storage capacity of the memory device.

Abstract

A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

MEMORY BLOCK CHARACTERISTIC DETERMINATION (17831350)

Main Inventor

Zhongyuan Lu

Brief explanation

The abstract of the patent application describes a method for determining the temperature of memory blocks in a memory device and allocating them for data storage based on their temperature.

• The method involves allocating memory blocks for data storage in a memory device.
• The temperature of each memory block is measured.
• If the temperature of a memory block exceeds a threshold operational temperature, it is allocated for data storage.
• The method helps in optimizing the allocation of memory blocks based on their temperature.

Potential Applications

This technology can have various applications in the field of memory devices and data storage systems, including:

• Computer systems and servers that require efficient memory allocation.
• Data centers where temperature management is crucial for optimal performance.
• Mobile devices and smartphones to improve memory usage and prevent overheating.

Problems Solved

The technology addresses the following problems:

• Inefficient memory allocation in memory devices.
• Overheating of memory blocks, which can lead to performance degradation or failure.
• Lack of a systematic approach to optimize memory allocation based on temperature.

Benefits

The technology offers several benefits:

• Improved performance and reliability of memory devices.
• Efficient utilization of memory blocks based on their temperature.
• Prevention of overheating and potential damage to memory blocks.
• Enhanced overall system performance and energy efficiency.

Abstract

Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.

INTERFACES BETWEEN HIGHER VOLTAGE AND LOWER VOLTAGE WAFERS AND RELATED APPARATUSES AND METHODS (18315311)

Main Inventor

Michael A. Smith

Brief explanation

The patent application describes interfaces between higher voltage and lower voltage wafers, along with related apparatuses and methods. Here are the key points:

• The apparatus consists of a memory wafer and a logic wafer.
• The memory wafer has data storage elements and bitlines connected to them.
• Isolation devices are also present, connected to the bitlines.
• The logic wafer is bonded to the memory wafer and contains logic circuitry.
• The logic circuitry is connected to the bitlines through the isolation devices.
• The logic circuitry has a maximum voltage difference tolerance lower than the operational voltage difference between the operational voltage potential and a reference voltage potential of the logic circuitry.
• The method involves isolating the logic circuitry from the bitlines, applying the operational voltage potential to the data storage elements, and then electrically connecting the logic circuitry to the bitlines.

Potential applications of this technology:

• Integrated circuits and electronic devices that require interfaces between higher and lower voltage components.
• Memory systems that need to connect memory wafers with logic wafers operating at different voltage potentials.

Problems solved by this technology:

• Enabling the integration of memory wafers and logic wafers operating at different voltage potentials.
• Providing a reliable and efficient interface between higher and lower voltage components.

Benefits of this technology:

• Allows for the efficient transfer of data between memory wafers and logic wafers.
• Provides a reliable and robust interface that can withstand voltage differences.
• Enables the development of more advanced and integrated electronic devices.

Abstract

Interfaces between higher voltage and lower voltage wafers and related apparatuses and methods are disclosed. An apparatus includes a memory wafer and a logic wafer. Data storage elements of an array are configured to perform an operation responsive to an operational voltage potential. The memory wafer also includes bitlines electrically connected to the data storage elements and isolation devices electrically connected to the bitlines. The logic wafer is bonded to the memory wafer. The logic wafer includes logic circuitry electrically connected to the bitlines through the isolation devices. A maximum voltage potential difference tolerance of the logic circuitry is less than an operational voltage potential difference between the operational voltage potential and a reference voltage potential of the logic circuitry. A method includes isolating the logic circuitry from the bitlines, applying the operational voltage potential the data storage elements, and electrically connecting the logic circuitry to the bitlines.

MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES (17860690)

Main Inventor

Mustafa N. Kaynak

Brief explanation

The abstract of this patent application describes a method for increasing the read window budget (RWB) in a memory access operation. The method involves selecting a target RWB increase and identifying a set of aggressor memory cells. A list of programming level states for the aggressor memory cells is generated, and an entry associated with a maximum RWB increase that meets or exceeds the target RWB increase is identified in the list. The method further involves modifying a parameter of the memory access operation based on the adjustment associated with the identified entry.

• Method for increasing the read window budget (RWB) in a memory access operation
• Selecting a target RWB increase
• Identifying a set of aggressor memory cells
• Generating a list of programming level states for the aggressor memory cells
• Identifying an entry in the list with a maximum RWB increase that meets or exceeds the target RWB increase
• Modifying a parameter of the memory access operation based on the adjustment associated with the identified entry

Potential applications of this technology:

• Memory access operations in computer systems
• Data storage and retrieval in electronic devices
• Improving the performance and efficiency of memory operations

Problems solved by this technology:

• Limited read window budget in memory access operations
• Difficulty in optimizing memory access performance
• Inefficient use of memory resources

Benefits of this technology:

• Increased read window budget for improved memory access performance
• Optimization of memory operations for better efficiency
• Enhanced utilization of memory resources

Abstract

Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME (17938153)

Main Inventor

Murong Lang

Brief explanation

The patent application describes methods, apparatuses, and systems for protecting an apparatus against unauthorized accesses or usages. The protection is achieved through a data protection circuit that safeguards the operating state and stored data of the apparatus when the temperature exceeds its operating range.

• The patent application focuses on protecting an apparatus from unauthorized accesses or usages.
• The apparatus includes a data protection circuit that safeguards the operating state and stored data.
• The protection is specifically activated when the temperature of the apparatus goes beyond its operating range.

Potential Applications

This technology can find applications in various fields where the protection of apparatuses and their data is crucial. Some potential applications include:

• Data centers and server rooms where temperature fluctuations can occur.
• Industrial equipment and machinery that operate in extreme temperature environments.
• Military and defense systems that require secure operation in harsh conditions.
• Medical devices and equipment that need protection against unauthorized access.

Problems Solved

The technology addresses the following problems:

• Unauthorized accesses or usages of apparatuses can lead to data breaches or system malfunctions.
• Temperature fluctuations can affect the operating state and stored data of an apparatus.
• Existing protection mechanisms may not be sufficient to safeguard apparatuses in extreme temperature conditions.

Benefits

The technology offers several benefits:

• Enhanced security by protecting against unauthorized accesses or usages.
• Safeguards the operating state and stored data of an apparatus.
• Provides protection even in extreme temperature environments.
• Helps prevent data breaches and system malfunctions.
• Can be applied to various apparatuses in different industries.

Abstract

Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

CELL VOLTAGE DROP COMPENSATION CIRCUIT (17831266)

Main Inventor

Kijun Nam

Brief explanation

The patent application describes a circuit that includes various components such as a memory cell, a source follower, a voltage source, an operational amplifier, and a replica source follower. These components are interconnected to perform certain functions within the circuit.

• The circuit includes a memory cell, which is a component used to store and retrieve data.
• A source follower is connected to the memory cell, allowing the memory cell to communicate with other parts of the circuit.
• A voltage source is used to provide a stable voltage reference for the circuit.
• An operational amplifier is included in the circuit, with its non-inverting input connected to the voltage source. The operational amplifier amplifies the voltage difference between its inputs.
• A replica source follower is connected to the output of the operational amplifier and its source terminal is connected to the inverting input of the operational amplifier via a feedback loop. This configuration helps in achieving certain desired characteristics or performance of the circuit.

Potential Applications

• This circuit design can be used in various electronic devices that require memory storage and retrieval, such as computers, smartphones, and other digital devices.
• It can be utilized in integrated circuits for data processing, signal amplification, or other applications where memory cells and operational amplifiers are needed.

Problems Solved

• The circuit provides a solution for integrating memory cells and operational amplifiers in a compact and efficient manner.
• It addresses the challenge of achieving desired performance characteristics, such as stability and amplification, in a circuit design.

Benefits

• The circuit design allows for efficient communication between memory cells and other components of the circuit.
• It provides stability and amplification capabilities through the use of operational amplifiers.
• The compact design of the circuit enables integration into various electronic devices, saving space and reducing manufacturing costs.

Abstract

In some aspects, the techniques described herein relate to a circuit including: a memory cell; a source follower, a source terminal of the source follower communicatively coupled to the memory cell; a voltage source; an operational amplifier, a non-inverting input of the operational amplifier communicatively coupled to the voltage source; and a replica source follower, a gate of the replica source follower communicatively coupled to an output of the operational amplifier and a source terminal of the replica source follower communicatively coupled to an inverting input of the operational amplifier via a feedback loop.

MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES (17860711)

Main Inventor

Mustafa N. Kaynak

Brief explanation

The abstract of this patent application describes a method for improving the read window budget (RWB) of memory cells in a computer system. The method involves identifying groups of wordlines, determining the maximum increase in RWB for each group, and calculating a target aggregate RWB increase. The method also involves determining the minimum number of memory cell programming level groups needed to reach the target RWB increase, and applying voltage offsets during memory cell access operations based on the specific programming level group containing the target programming level.

• Identifying wordline groups and corresponding default program verify (PV) voltages
• Determining maximum RWB increase for each wordline group
• Calculating a target aggregate RWB increase
• Determining minimum number of programming level groups needed to reach the target RWB increase
• Applying voltage offsets during memory cell access operations based on the specific programming level group containing the target programming level

Potential Applications

• This technology can be applied in computer systems that use memory cells, such as solid-state drives (SSDs) and random-access memory (RAM).
• It can improve the performance and reliability of memory cells by optimizing the read window budget.

Problems Solved

• Memory cells in computer systems often have limited read window budgets, which can lead to errors and reduced performance.
• This technology solves the problem by dynamically adjusting the programming levels and voltages of memory cells to increase the read window budget.

Benefits

• Improved performance and reliability of memory cells in computer systems.
• Increased read window budget allows for more accurate and efficient reading of data from memory cells.
• Dynamic adjustment of programming levels and voltages optimizes the read window budget, leading to better overall system performance.

Abstract

Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.

ADAPTIVE CALIBRATION FOR THRESHOLD VOLTAGE OFFSET BINS (18204189)

Main Inventor

Vamsi Pavan Rayaprolu

Brief explanation

The patent application describes a system that includes a memory device and a processing device. The system performs operations to determine if a program erase cycle count associated with a segment of the memory device meets a certain threshold criterion. If it does, the system performs a calibration measurement of the voltage valley center for each state of each cell in the segment. Based on the result of the calibration measurement, the system updates a threshold voltage offset bin associated with the segment of the memory device.

• The system determines if a program erase cycle count meets a threshold criterion.
• If it does, the system performs a calibration measurement of the voltage valley center for each state of each cell in the memory segment.
• Based on the calibration measurement, the system updates a threshold voltage offset bin associated with the memory segment.

Potential Applications

• This technology can be applied in various memory devices, such as flash memory, to improve performance and reliability.
• It can be used in data storage systems to enhance data retention and endurance.

Problems Solved

• The system solves the problem of maintaining accurate threshold voltage offset bins in memory devices.
• It addresses the issue of program erase cycle count affecting the performance and reliability of memory devices.

Benefits

• By updating the threshold voltage offset bins, the system improves the accuracy and efficiency of memory operations.
• The calibration measurement helps in maintaining the integrity of data stored in memory devices.
• This technology extends the lifespan of memory devices by optimizing their performance and endurance.

Abstract

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: determining whether a program erase cycle count associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update; responsive to determining that the program erase cycle count satisfies the first threshold creation, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device; and updating a threshold voltage offset bin associated with the segment of the memory device based on a result of the calibration measurement.

MEMORY SECTION SELECTION FOR A MEMORY BUILT-IN SELF-TEST (17807303)

Main Inventor

Scott E. SCHAEFER

Brief explanation

The abstract describes a method for selecting memory sections for a memory built-in self-test (BIST) in a memory device. Here is a simplified explanation of the abstract:

• The memory device reads a set of bits from a test control mode register to determine the test mode for performing the memory BIST.
• The memory device then reads another set of bits from a section identifier mode register to identify the specific memory sections for which the BIST is to be performed.
• The memory sections selected for the BIST are a subset of the total memory sections in the memory device.
• Finally, the memory device performs the BIST for the selected memory sections based on the test mode.

Potential Applications:

• Memory testing: This technology can be applied in various memory devices, such as RAM, to perform built-in self-tests on specific memory sections, ensuring their proper functioning.
• Quality control: By selectively testing specific memory sections, manufacturers can identify and address any issues or defects in those sections, improving the overall quality of the memory device.

Problems Solved:

• Efficient testing: By allowing the selection of specific memory sections for testing, this technology enables more targeted and efficient memory testing, saving time and resources.
• Fault isolation: By identifying and testing specific memory sections, any faults or failures can be isolated to those sections, making it easier to diagnose and fix issues.

Benefits:

• Customizable testing: The ability to select specific memory sections for testing provides flexibility and customization in the memory BIST process.
• Resource optimization: By testing only the necessary memory sections, resources such as time and power can be optimized, reducing testing overhead.
• Improved reliability: By performing targeted tests on specific memory sections, any potential issues can be identified and resolved, leading to improved overall reliability of the memory device.

Abstract

Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.

REFRESH RATE SELECTION FOR A MEMORY BUILT-IN SELF-TEST (17807307)

Main Inventor

Scott E. SCHAEFER

Brief explanation

The patent application describes a method for selecting a refresh rate for a memory built-in self-test (BIST) in a memory device. 

• The memory device reads one or more bits stored in a mode register to determine the refresh rate for the memory BIST.
• The refresh rate indicates how often the memory cells to be tested by the BIST should be refreshed during the test.
• The memory device performs the memory BIST while refreshing the memory cells according to the selected refresh rate.

Potential Applications

• This technology can be applied in various memory devices, such as computer RAM, to improve the efficiency and accuracy of built-in self-tests.
• It can be used in manufacturing processes to ensure the quality and reliability of memory devices before they are shipped to customers.

Problems Solved

• Traditional memory BIST methods may not consider the impact of refresh rates on the accuracy of the test results.
• Inadequate refresh rates during memory BIST can lead to errors or false positives/negatives, affecting the reliability of the memory device.

Benefits

• By dynamically selecting the refresh rate based on the mode register bits, the memory BIST can be optimized for accuracy and efficiency.
• The technology ensures that the memory cells being tested are refreshed at an appropriate rate, minimizing the risk of errors during the test.
• It improves the overall quality and reliability of memory devices, leading to better performance and customer satisfaction.

Abstract

Implementations described herein relate to refresh rate selection for a memory built-in self-test. A memory device may read one or more bits, associated with the memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, a refresh rate to be used while performing the memory built-in self-test. The refresh rate may indicate a rate at which memory cells, to be tested by the memory built-in self-test, are to be refreshed while the memory built-in self-test is being performed. The memory device may perform the memory built-in self-test while refreshing the memory cells according to the refresh rate.

LOOPBACK DATAPATH FOR CLOCK QUALITY DETECTION (18312280)

Main Inventor

Matthew Alan Prather

Brief explanation

The patent application describes devices and methods for monitoring the operation of a memory device by transmitting loopback signals. Here is a simplified explanation of the abstract:

• Memory devices can monitor their own operation by generating loopback signals.
• The memory device receives a system clock signal from a host device and generates an internal clock signal based on it.
• The memory device then generates a loopback signal based on the internal clock signal and transmits it through a loopback datapath.
• The host device compares the internal clock signal with the system clock signal to determine the accuracy of the internal clock signal.
• The termination values of the memory device can be adjusted based on the fidelity of the internal clock signal.

Potential applications of this technology:

• Memory device testing and debugging: The loopback signals can be used to monitor the operation of memory devices during testing and debugging processes.
• Performance optimization: By adjusting the termination values based on the fidelity of the internal clock signal, the memory device's performance can be optimized.

Problems solved by this technology:

• Monitoring memory device operation: The loopback signals provide a way to monitor the operation of memory devices and identify any potential issues or inaccuracies.
• Clock signal fidelity determination: By comparing the internal clock signal with the system clock signal, the accuracy of the internal clock signal can be determined.

Benefits of this technology:

• Improved memory device performance: By adjusting the termination values based on the fidelity of the internal clock signal, the memory device can operate more efficiently and reliably.
• Enhanced testing and debugging capabilities: The loopback signals allow for better monitoring and analysis of memory device operation, facilitating faster and more accurate testing and debugging processes.

Abstract

Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS (18205083)

Main Inventor

Jian Huang

Brief explanation

The abstract describes a method for determining and optimizing the quality characteristics of memory dice in a memory device. The method involves binning information related to the quality characteristics of each memory dice and performing a select gate scan to determine threshold voltages and windows. Based on the determined quality characteristics, an erase and program operation is performed to set a second threshold voltage and window for a subset of memory dice.

• The method determines and categorizes the quality characteristics of memory dice in a memory device.
• A select gate scan is performed to determine the first threshold voltage and window for each memory dice.
• Based on the quality characteristics, a subset of memory dice is identified for optimization.
• An erase and program operation is performed to set a second threshold voltage and window for the identified subset.
• The second threshold voltage window is greater than the first threshold voltage window.

Potential Applications

• Memory device manufacturing and optimization.
• Quality control in memory device production.
• Improving the performance and reliability of memory devices.

Problems Solved

• Inefficient optimization of memory dice in a memory device.
• Lack of a systematic approach to determine and optimize quality characteristics.
• Difficulty in achieving desired threshold voltage and window for memory dice.

Benefits

• Enhanced quality control and optimization of memory devices.
• Improved performance and reliability of memory devices.
• Efficient and systematic approach to determine and set threshold voltages and windows.

Abstract

A method includes determining, for a plurality of memory dice, binning information relating to quality characteristics of each of the plurality of memory dice. The method further includes performing a select gate scan to determine a first threshold voltage and a first threshold voltage window of each of the plurality of memory dice, and, based on the determined quality characteristics of each of the plurality of memory dice, perform an erase and program operation to set a second threshold voltage with a second threshold voltage window of a subset of memory dice among the plurality of memory dice where the second threshold voltage window is greater than the first threshold voltage window.

ENABLING OR DISABLING ON-DIE ERROR-CORRECTING CODE FOR A MEMORY BUILT-IN SELF-TEST (17807314)

Main Inventor

Scott E. SCHAEFER

Brief explanation

The patent application describes a method for enabling or disabling on-die error-correcting code (ECC) for a memory built-in self-test. Here are the key points:

• The memory device reads bits stored in a mode register to determine whether the memory built-in self-test should be performed with on-die ECC disabled or enabled.
• Based on the identified mode, the memory device performs the memory built-in self-test and selectively tests for single-bit errors.
• The on-die ECC can be disabled or enabled during the memory built-in self-test, allowing for flexibility in testing and error correction.

Potential applications of this technology:

• Memory testing: This method can be used in memory devices to perform built-in self-tests and identify single-bit errors, helping to ensure the reliability of memory systems.
• Error correction: By selectively enabling or disabling on-die ECC during the self-test, this technology allows for targeted testing and error correction, improving the efficiency of error correction mechanisms.

Problems solved by this technology:

• Flexibility in testing: By providing the option to enable or disable on-die ECC during the self-test, this method allows for different testing scenarios and strategies, depending on the specific requirements of the memory device.
• Efficient error correction: By selectively testing for single-bit errors based on the identified mode, this technology optimizes the error correction process, focusing on the most relevant errors and reducing unnecessary overhead.

Benefits of this technology:

• Improved reliability: By performing built-in self-tests and selectively testing for single-bit errors, this method helps to identify and correct memory errors, enhancing the overall reliability of memory systems.
• Enhanced efficiency: The ability to enable or disable on-die ECC during the self-test allows for targeted testing and error correction, improving the efficiency of memory testing and error correction mechanisms.

Abstract

Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

INTERRUPTING A MEMORY BUILT-IN SELF-TEST (17808043)

Main Inventor

Scott E. SCHAEFER

Brief explanation

The patent application describes a method for interrupting a memory built-in self-test (BIST) in a memory device. Here are the key points:

• The memory device reads one or more bits stored in a mode register to determine if the memory BIST should be interrupted.
• The memory device can identify, based on these bits, whether the BIST should be interrupted while it is being performed in a test mode.
• However, the memory device is not allowed to interrupt the BIST if it is being performed in a repair mode.
• If the conditions are met, the memory device interrupts the BIST while it is being performed in the test mode.

Potential applications of this technology:

• Memory testing: This method can be used in memory devices to interrupt the built-in self-test during the testing phase, allowing for more efficient testing processes.
• Manufacturing: The ability to interrupt the BIST can be useful during the manufacturing process to quickly identify and address any issues with the memory device.

Problems solved by this technology:

• Efficient testing: By allowing the memory device to interrupt the BIST during the test mode, unnecessary testing time can be saved, improving overall efficiency.
• Flexibility: The ability to interrupt the BIST based on the mode register bits provides flexibility in controlling the testing process based on specific requirements.

Benefits of this technology:

• Time-saving: Interrupting the BIST during the test mode can save significant testing time, especially in large-scale memory testing scenarios.
• Improved control: The mode register bits allow for better control over the testing process, ensuring that the BIST is interrupted only when necessary and not during the repair mode.

Abstract

Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

GLITCH DETECTION REDUNDANCY (17831329)

Main Inventor

Angelo Alberto Rovelli

Brief explanation

The abstract describes a method for detecting and notifying glitches in a memory system to multiple processing units.

• The method involves using a glitch detector connected to a first processing unit to detect glitches in a memory system.
• Once a glitch is detected, the method notifies at least a second processing unit about the glitch using a connection matrix.
• After receiving the notification, the second processing unit transmits a glitch confirmation signal.

Potential applications of this technology:

• This method can be used in computer systems to detect and notify glitches in memory systems, ensuring the reliability and stability of the system.
• It can be applied in embedded systems, where glitches in memory can cause malfunctions or data corruption, leading to system failures.
• This technology can also be useful in high-performance computing systems, where glitches can impact the accuracy and efficiency of computations.

Problems solved by this technology:

• Glitches in memory systems can lead to data corruption, system crashes, or incorrect results in computations. This method helps in quickly detecting and notifying glitches, allowing for timely actions to mitigate their impact.
• By notifying multiple processing units about glitches, this method enables coordinated responses and ensures that all relevant components are aware of the issue.

Benefits of this technology:

• Improved system reliability: By promptly detecting and notifying glitches, this method helps in preventing system failures and data corruption.
• Efficient troubleshooting: The glitch confirmation signal transmitted by the second processing unit can aid in identifying the root cause of the glitch, facilitating faster troubleshooting and resolution.
• Coordinated response: Notifying multiple processing units ensures that all relevant components are informed, enabling coordinated actions to address the glitch and minimize its impact.

Abstract

A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

DIFFERENTIAL STROBE FAULT INDICATION (17862082)

Main Inventor

Scott E. Schaefer

Brief explanation

The patent application describes methods, systems, and devices for indicating faults in memory devices using a read strobe signal. The read strobe signal can be a true RDQS signal or a complement RDQS signal. The memory device can indicate a fault based on characteristics of the read strobe signal, such as its pattern, voltage level, or the difference between two read strobe signals. The host device can instruct the memory device on which characteristic to use for fault indication.

• Memory devices can indicate faults using a read strobe signal
• The read strobe signal can be a true RDQS or a complement RDQS signal
• Fault indication can be based on characteristics of the read strobe signal
• Characteristics can include the pattern, voltage level, or difference between two read strobe signals
• The host device can instruct the memory device on which characteristic to use for fault indication

Potential Applications

• Memory devices in various electronic devices
• Fault detection and indication in memory systems

Problems Solved

• Efficient fault detection in memory devices
• Clear indication of faults using read strobe signals

Benefits

• Improved reliability of memory devices
• Quick and accurate fault detection
• Simplified fault indication process

Abstract

Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the fault.

ERROR DETECTION FOR A SEMICONDUCTOR DEVICE (17889369)

Main Inventor

Matthew Young

Brief explanation

The present disclosure is about a technology for error detection in a semiconductor device. It includes an apparatus with a memory array, a detector array, and a detector. The detector is designed to identify errors in a portion of the detector array and send an output signal to memory components connected to the detector array when an error is detected.

• The technology is focused on error detection for a semiconductor device.
• The apparatus consists of a memory array, a detector array, and a detector.
• The detector is responsible for detecting errors in a specific part of the detector array.
• When an error is detected, the detector sends an output signal to the memory components connected to the detector array.

Potential Applications

This technology can have various applications in the field of semiconductor devices, including:

• Integrated circuits
• Microprocessors
• Memory modules
• Data storage devices

Problems Solved

The technology addresses the following problems:

• Error detection in semiconductor devices
• Ensuring the accuracy and reliability of data stored in memory arrays
• Identifying and isolating faulty portions of a detector array

Benefits

The technology offers several benefits, such as:

• Improved error detection capabilities in semiconductor devices
• Enhanced reliability and accuracy of data stored in memory arrays
• Efficient identification and isolation of errors in the detector array
• Facilitates prompt response and corrective actions for detected errors.

Abstract

The present disclosure includes apparatus, methods, and systems for error detection for a semiconductor device. An apparatus includes a memory array, a detector array, and a detector coupled to the detector array. The detector is configured to detect an error in a portion of the detector array and output an output signal to memory components coupled to the detector array in response to detecting the error.

POST PACKAGE REPAIR MANAGEMENT (17959191)

Main Inventor

Danilo Caraccio

Brief explanation

The abstract describes a method for repairing a soft post package in a memory array. Here is a simplified explanation of the abstract:

• When a soft post package repair (sPPR) request is detected, data from a specific row in the memory array is stored in a buffer.
• Execution of non-maintenance requests on the same row is temporarily stopped.
• The sPPR request is then executed on the target row.
• Once the sPPR request is completed, execution of non-maintenance requests on the target row is resumed.
• The data stored in the buffer is written back to the repaired target row.

Potential Applications

This technology could be applied in various industries and sectors where memory arrays are used, such as:

• Computer systems and servers
• Mobile devices and smartphones
• Data centers and cloud computing
• Internet of Things (IoT) devices
• Automotive electronics

Problems Solved

The technology addresses the following problems:

• Soft post package repairs in memory arrays can lead to data loss or corruption if not handled properly.
• Suspending execution of non-maintenance requests on the target row ensures that the repair process is not interrupted or affected by other operations.
• Storing the data in a buffer prevents loss of information during the repair process.

Benefits

The use of this technology offers several benefits:

• Improved reliability and integrity of data in memory arrays.
• Minimized risk of data loss or corruption during soft post package repairs.
• Efficient and effective repair process without impacting normal operations.
• Enhanced performance and longevity of memory arrays.

Abstract

A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

MULTI-COIL INDUCTION APPARATUS (18203735)

Main Inventor

Timothy Hollis

Brief explanation

The patent application describes a multi-coil induction apparatus that includes a primary coil structure and a secondary coil structure. 

• The primary coil structure consists of a primary first coil portion and a primary second coil portion, both located on the same flat surface.
• The secondary coil structure includes a secondary first coil portion and a secondary second coil portion, which are also on the same flat surface and parallel to the primary coil structure.
• The primary first coil portion and the secondary first coil portion are concentrically wound on the common flat surface, creating a coupled induction section.
• The primary second coil portion and the secondary second coil portion are positioned adjacent to the coupled induction section on the same flat surface.

Potential applications of this technology:

• Wireless power transfer systems
• Inductive charging for electric vehicles
• Inductive heating systems
• Inductive communication systems

Problems solved by this technology:

• Improved efficiency of power transfer
• Enhanced coupling between primary and secondary coils
• Simplified design and manufacturing process

Benefits of this technology:

• Increased power transfer efficiency
• Reduced energy loss
• Compact and space-saving design
• Cost-effective production process

Abstract

Systems, methods and apparatus are provided for a multi-coil induction apparatus. The multi-coil induction apparatus has a primary coil structure with a primary first coil portion and a primary second coil portion where both are on a common planar surface; and a secondary coil structure having a secondary first coil portion and a secondary second coil, where the secondary first coil portion and the secondary second coil portion are coplanar with the primary first coil portion and the primary second coil. The primary first coil portion and the secondary first coil portion concentrically turn on the common planar surface to form a coupled induction section while the primary second coil portion and the secondary second coil portion are adjacent the coupled induction section on the common planar surface.

SELECTIVE CAVITY MERGING FOR ISOLATION REGIONS IN A MEMORY DIE (17863317)

Main Inventor

Yoshiaki Fukuzumi

Brief explanation

The patent application describes methods, systems, and devices for selectively merging cavities in isolation regions of a memory die. Here is a simplified explanation of the abstract:

• The formation of material structures in a memory die involves depositing alternating layers of two different materials over a substrate.
• Cavities are then formed through the stack of alternating material layers.
• Portions of the second material are removed to create voids between layers of the first material.
• To create an electrical isolation region, a dielectric material is deposited in some of the cavities and in a portion of the voids between the layers of the first material.

Potential Applications:

• Memory devices: This technology can be applied to improve the isolation regions in memory dies, leading to enhanced performance and reliability of memory devices.

Problems Solved:

• Improved isolation: The selective cavity merging technique helps in creating effective electrical isolation regions in memory dies, reducing the risk of interference and improving overall device performance.

Benefits:

• Enhanced performance: The improved isolation regions result in better signal integrity and reduced noise, leading to enhanced performance of memory devices.
• Increased reliability: The selective cavity merging technique helps in minimizing cross-talk and interference, improving the reliability and stability of memory devices.

Abstract

Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.

SINGULATED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS (18140523)

Main Inventor

Marc Anthony Romana de Guzman

Brief explanation

A semiconductor device is described in this patent application. It involves a semiconductor substrate that is separated from a device wafer containing multiple semiconductor devices. The substrate has a first corner and two sidewalls extending from the corner in different directions. 

• The first sidewall has a laser modification along its direction.
• The second sidewall also has a laser modification along its direction.
• The portion of the second sidewall between the first corner and the second laser modification can either have no laser modification or the second laser modification can be offset from the first corner.

Potential Applications:

• Semiconductor manufacturing
• Electronics industry

Problems Solved:

• Efficient singulation of semiconductor substrates from device wafers
• Precise laser modifications on sidewalls

Benefits:

• Improved accuracy and control in semiconductor device manufacturing
• Enhanced performance and reliability of semiconductor devices

Abstract

A semiconductor device can include a semiconductor substrate singulated from a device wafer having had multiple semiconductor devices formed thereon. The semiconductor substrate can include a first corner, a first sidewall extends in a first direction from the first corner, and a second sidewall extending in a second direction from the first corner. The first sidewall can include a first laser modification extending along the first direction and the second sidewall can include a second laser modification extending along the second direction. A portion of the second sidewall between the first corner and the second laser modification can (i) exclude laser modification, or (ii) the second laser modification can be offset from the first corner along the second direction.

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS (18454703)

Main Inventor

Sameer S. Vadhavkar

Brief explanation

The abstract describes a method for packaging a semiconductor die assembly. The method involves coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The thermal transfer structure limits the lateral flow of the underfill material.

• The method involves packaging a semiconductor die assembly with a first die and multiple second dies stacked on top of it.
• The first die has a peripheral region extending outward from the stack of second dies.
• A thermal transfer structure is attached to the peripheral region of the first die.
• An underfill material is then flowed between the second dies.
• The thermal transfer structure prevents the underfill material from flowing laterally.

Potential applications of this technology:

• Semiconductor packaging industry
• Electronics manufacturing

Problems solved by this technology:

• Prevents lateral flow of underfill material, which can cause damage or malfunction in the semiconductor die assembly.

Benefits of this technology:

• Improved reliability and performance of semiconductor die assemblies
• Enhanced thermal management
• Reduced risk of damage or malfunction due to underfill material flow.

Abstract

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Memory Circuitry And Method Used In Forming Memory Circuitry (17851393)

Main Inventor

Jivaan Kishore Jhothiraman

Brief explanation

The patent application describes a memory circuitry that consists of strings of memory cells arranged in a stack. The stack is made up of alternating layers of insulative and conductive tiers. The memory cells extend through these layers in a memory-array region.

• The memory circuitry is made up of strings of memory cells arranged in a stack.
• The stack consists of alternating layers of insulative and conductive tiers.
• The memory cells extend through these layers in a memory-array region.

The stack extends into a stair-step region, which includes a cavity with a flight of stairs in a vertical cross-section. The cavity is filled with insulating material, with the treads of the stairs made of a conducting material from the conductive tiers.

• The stack extends into a stair-step region with a cavity that has a flight of stairs.
• The cavity is filled with insulating material, with the treads of the stairs made of conducting material.

The insulating material in the cavity is composed of two different materials. The first material is on top of the treads of the stairs, while the second material is directly above the first material. The first material is lower in height than the second material.

• The insulating material in the cavity is made up of two different materials.
• The first material is on top of the treads of the stairs, and the second material is directly above the first material.
• The first material is lower in height than the second material.

Conductive vias extend through both the first and second materials, with each via directly above and in contact with the conducting material of the respective tread.

• Conductive vias go through both the first and second materials.
• Each via is directly above and in contact with the conducting material of the respective tread.

Potential applications of this technology:

• Memory circuitry for electronic devices
• Data storage systems

Problems solved by this technology:

• Efficient arrangement of memory cells in a stack
• Improved insulation and conductivity in memory circuitry

Benefits of this technology:

• Higher memory capacity in a compact design
• Enhanced performance and reliability of memory circuitry

Abstract

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs in a first vertical cross-section along a first direction. Insulating material is in the cavity above the flight of stairs. The insulating material comprises first material atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Insulative second material of different composition from that of the first material is directly above the first material. The first material has an uppermost surface in the cavity that is below an uppermost surface of the insulative second material in the cavity. Conductive vias extend through the first material and the insulative second material. Individual of the conductive vias are directly above and directly against the conducting material of the respective tread. Other embodiments, including method, are disclosed.

MEMORY DEVICE INCLUDING SOURCE STRUCTURE HAVING CONDUCTIVE ISLANDS OF DIFFERENT WIDTHS (18202061)

Main Inventor

Shuangqiang Luo

Brief explanation

The patent application describes an apparatus that includes a conductive structure with multiple conductive regions and islands, as well as dielectric isolators. The conductive islands are separated from each other and have different portions on either side.

• The apparatus includes a conductive structure with multiple conductive regions and islands.
• The conductive islands are separated from each other and have different portions on either side.
• Dielectric isolators are used to separate the conductive islands.
• The width of the conductive island is greater than the width of at least one conductive island in each portion.

Potential applications of this technology:

• Memory devices
• Integrated circuits
• Semiconductor devices

Problems solved by this technology:

• Improved conductivity and performance of memory cells
• Enhanced isolation between conductive islands

Benefits of this technology:

• Increased efficiency and reliability of memory devices
• Better control over the conductive structure
• Improved overall performance of integrated circuits and semiconductor devices.

Abstract

Some embodiments include apparatuses. One of the apparatuses includes a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions; conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region; dielectric isolators separating the conductive islands from each other, wherein the conductive islands include a conductive island such that a first portion of the conductive islands is located on a first side of the conductive island, and a second portion of the conductive islands is located on a second side of the conductive island; and the width of the conductive island is greater than the width of at least one conductive island in each of the first and second portions of the conductive islands.

MICROELECTRONIC DEVICES COMPRISING A BORON-CONTAINING MATERIAL, AND RELATED ELECTRONIC SYSTEMS AND METHODS (17822726)

Main Inventor

Xiao Li

Brief explanation

The patent application describes a microelectronic device that includes a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure consists of alternating conductive structures and dielectric structures, while the contact structure extends through the stack structure. The liner material is positioned between the stack structure and the contact structure, and the boron-containing material is located between the liner material and the stack structure.

• The microelectronic device includes a stack structure with alternating conductive and dielectric structures.
• A contact structure extends through the stack structure.
• A liner material is positioned between the stack structure and the contact structure.
• A boron-containing material is located between the liner material and the stack structure.

Potential Applications:

• This microelectronic device can be used in various electronic systems, such as integrated circuits, microprocessors, and memory devices.
• It can be applied in the manufacturing of electronic devices for consumer electronics, telecommunications, automotive, aerospace, and other industries.

Problems Solved:

• The use of the liner material and boron-containing material helps to improve the performance and reliability of the microelectronic device.
• It addresses issues related to electrical conductivity, insulation, and contact resistance in the stack structure.

Benefits:

• The improved performance and reliability of the microelectronic device can lead to enhanced functionality and efficiency in electronic systems.
• The use of the liner material and boron-containing material can contribute to the miniaturization and integration of electronic components, enabling smaller and more advanced devices.

Abstract

A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (17805221)

Main Inventor

Shuangqiang Luo

Brief explanation

The patent application describes a microelectronic device with a stack structure that includes alternating layers of conductive and insulative materials. The stack structure is divided into blocks by filled slot structures. Each block consists of a memory array region, staircase structures with steps, and crest regions between neighboring staircase structures. The device also includes contact structures that extend vertically through the stack structure to a source tier below.

• The microelectronic device has a stack structure with alternating layers of conductive and insulative materials.
• The stack structure is divided into blocks by filled slot structures.
• Each block includes a memory array region, staircase structures, and crest regions.
• Contact structures extend vertically through the stack structure to a source tier below.
• The contact structures include first contact structures in electrical communication with control logic circuitry.
• The contact structures also include second contact structures that are electrically isolated from the control logic circuitry.
• Some of the first contact structures are positioned more centrally within each block in a horizontal direction compared to some of the second contact structures.

Potential Applications

• Microelectronic devices with improved memory array regions.
• Devices with efficient contact structures for control logic circuitry.

Problems Solved

• Efficient organization and arrangement of memory array regions in microelectronic devices.
• Improved contact structures for control logic circuitry.

Benefits

• Enhanced performance and functionality of microelectronic devices.
• Increased efficiency in accessing and controlling memory array regions.
• Improved integration of control logic circuitry.

Abstract

A microelectronic device includes a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks by filled slot structures, each of the blocks comprising: a memory array region; staircase structures having steps; and crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures, and contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures comprising: first contact structures in electrical communication with control logic circuitry; and second contact structures electrically isolated from the control logic circuitry, at least some the first contact structures relatively more centrally positioned with each of the blocks in a second horizontal direction orthogonal to the first horizontal direction than at least some of the second contact structures.

MICROELECTRONIC DEVICES WITH CONTACTS EXTENDING THROUGH METAL OXIDE REGIONS OF STEP TREADS, AND RELATED SYSTEMS AND METHODS (17812141)

Main Inventor

Mithun Kumar Ramasahayam

Brief explanation

The patent application describes a microelectronic device that consists of a stack with alternating insulative and conductive structures arranged in tiers. Within the stack, there is a staircased stadium with steps at different tier elevations.

• The steps in the staircased stadium are formed by the upper surface area of a conductive structure and a metal oxide region that extends through the conductive structure.
• A pair of conductive contact structures extends to one of the steps.
• One of the contact structures terminates at the tread of the step, within the area of the conductive structure.
• The other contact structure extends through the tread of the step, within the upper surface area of the metal oxide region.

Potential applications of this technology:

• Microelectronic devices and systems
• Integrated circuits
• Semiconductor devices

Problems solved by this technology:

• Provides a structure for efficient electrical contact in microelectronic devices
• Allows for vertical integration of insulative and conductive structures
• Enables precise control of electrical connections within the device

Benefits of this technology:

• Improved performance and functionality of microelectronic devices
• Enhanced electrical contact reliability
• Increased integration density in semiconductor devices

Abstract

Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.

TECHNIQUES FOR CONCURRENTLY-FORMED CAVITIES IN THREE-DIMENSIONAL MEMORY ARRAYS (17816505)

Main Inventor

Yoshiaki Fukuzumi

Brief explanation

The patent application describes methods, systems, and devices for creating cavities in three-dimensional memory arrays. These cavities are formed during the manufacturing process of a memory die and are used to create different features of the memory device.

• The cavities are formed through material removal operations, allowing for the creation of various structures within the memory die.
• A sacrificial region is formed using material addition or removal operations, which includes openings that support the formation of different memory device structures.
• Once the structures are formed, the sacrificial region is isolated from the active region by merging a subset of the previously-formed cavities.

Potential Applications

• This technology can be applied in the manufacturing of three-dimensional memory arrays.
• It can be used to create complex memory device structures with multiple features.

Problems Solved

• This technology solves the problem of efficiently forming cavities in three-dimensional memory arrays.
• It allows for the creation of different memory device structures using a single set of cavities.

Benefits

• The concurrent formation of cavities simplifies the manufacturing process of memory dies.
• It enables the creation of complex memory device structures with improved efficiency.
• The ability to isolate the sacrificial region from the active region improves the overall performance and reliability of the memory device.

Abstract

Methods, systems, and devices for techniques for concurrently-formed cavities in three-dimensional memory arrays are described. As part of forming a memory die, a plurality of cavities may be formed by a set of one or more material removal operations, and different subsets of the plurality of cavities may be used to form different features of the memory die. In some examples, a sacrificial region may be formed in accordance with one or more material addition or removal operations, and such a sacrificial region may include openings that support the formation of various structures of a memory device. After the formation of such structures, the sacrificial region may be isolated from an active region by merging a subset of the previously-formed plurality of cavities.

MEMORY DEVICE INCLUDING HIGH-ASPECT-RATIO CONDUCTIVE CONTACTS (17848021)

Main Inventor

Shuangqiang Luo

Brief explanation

The patent application describes an apparatus and method for forming memory cells with control gates on different tiers. The apparatus includes memory cells, control gates, a dielectric structure, and conductive contacts.

• The apparatus includes memory cells located on different tiers.
• Control gates are located on respective tiers to control the memory cells.
• A dielectric structure is placed over the control gates.
• Two conductive contacts are formed in the dielectric structure, each contacting a different control gate.
• The first conductive contact has a certain length, while the second conductive contact has a different length.
• The second conductive contact is divided into two portions, with the second portion located between the first portion and the second control gate.
• The first portion of the second conductive contact has a certain width, while the second portion has a greater width.

Potential applications of this technology:

• Memory devices: The described apparatus can be used in memory devices to improve their performance and efficiency.
• Semiconductor industry: This technology can be applied in the semiconductor industry to enhance the design and functionality of memory cells.

Problems solved by this technology:

• Unequal lengths: The invention addresses the issue of having conductive contacts with unequal lengths, which can impact the performance and reliability of memory cells.
• Varying widths: The technology solves the problem of having different widths in different portions of the conductive contacts, ensuring proper electrical connections.

Benefits of this technology:

• Improved performance: The described apparatus can enhance the performance of memory cells by providing more precise and efficient control.
• Enhanced reliability: By addressing the issues of unequal lengths and varying widths, the technology improves the reliability and stability of memory cells.
• Design flexibility: The invention allows for different lengths and widths in conductive contacts, providing design flexibility for memory devices.

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes memory cells located on tiers; control gates for the memory cells and located on respective tiers; a dielectric structure over the control gates; a first conductive contact formed in the dielectric structure and contacting a first control gate, the first conductive contact having a first length; and a second conductive contact formed in the dielectric structure and contacting the second control gate, the second conductive contact having a second length unequal to the first length, wherein the second conductive contact includes a first portion and a second portion, the second portion is between the first portion and the second control gate, the first portion including a first region having a first width, the second portion including a second region having a second width, and the second width being greater than the first width.

Memory Circuitry And Method Used In Forming Memory Circuitry (17865565)

Main Inventor

Harsh Narendrakumar Jain

Brief explanation

The patent application describes a method for forming memory circuitry using a stack of alternating tiers. The stack extends from a memory-array region into a stair-step region, which has a flight of stairs in a vertical cross-section. 

• The method involves forming masking material directly above the flight of stairs.
• Ion implantation is used to create different-composition regions above each individual stair.
• One of the regions is selectively removed, leaving the other as a mask.
• The remaining region is used to etch through the tiers in each stair, creating multiple different-depth treads in the stairs.

Potential applications of this technology:

• Memory circuitry in electronic devices such as computers, smartphones, and tablets.
• Storage devices like solid-state drives and flash memory.

Problems solved by this technology:

• Efficient formation of memory circuitry with multiple different-depth treads.
• Improved performance and capacity of memory devices.

Benefits of this technology:

• Increased memory density and storage capacity.
• Enhanced performance and speed of memory devices.
• Cost-effective manufacturing process for memory circuitry.

Abstract

A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions. After the removing, the other of the first and second regions is used as a mask while etching through one of the first tiers and one of the second tiers in the individual stairs to form multiple different-depth treads in the individual stairs in a second vertical cross-section along the second direction. Other embodiments, including structure, are disclosed.

SEMICONDUCTOR MEMORY STACKS CONNECTED TO PROCESSING UNITS AND ASSOCIATED SYSTEMS AND METHODS (18452695)

Main Inventor

Kyle K. Kirby

Brief explanation

The patent application describes a semiconductor memory stack connected to a processing unit, along with associated methods and systems. The memory stack includes memory dies attached to a memory controller die, and the processing unit is attached to the memory controller die without an interposer. The memory stack and processing unit can be attached to a package substrate without an interposer as well.

• The semiconductor memory stack includes memory dies attached to a memory controller die.
• The processing unit is attached to the memory controller die without an interposer.
• The memory stack and processing unit can be attached to a package substrate without an interposer.

Potential Applications

This technology can be applied in various fields, including:

• Data centers
• High-performance computing
• Artificial intelligence and machine learning systems
• Gaming consoles
• Mobile devices

Problems Solved

This technology addresses several challenges in semiconductor memory systems, such as:

• Signal travel distance and latency between the memory stack and processing unit
• Complex interposer designs and manufacturing processes
• Cost and complexity associated with interposer integration

Benefits

The use of this technology offers several advantages, including:

• Shortest possible route for signals between the memory stack and processing unit
• Simplified design and manufacturing processes without the need for interposers
• Improved performance and reduced latency in memory systems
• Cost savings in production and integration of memory stacks and processing units

Abstract

A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING SUPPORT CONTACT STRUCTURES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17805009)

Main Inventor

Yiping Wang

Brief explanation

Methods of forming a microelectronic device are described in this patent application. The process involves creating a preliminary stack structure with blocks separated by slots. Each block consists of tiers made of insulative and sacrificial materials, with live contact openings and support contact openings extending through the tiers. 

Here are the key points of the patent/innovation:

• Formation of a preliminary stack structure with blocks and slots.
• Tiers within each block consisting of insulative and sacrificial materials.
• Live contact openings and support contact openings extending through the tiers.
• Formation of first and second liners over the preliminary stack structure.
• Removal of portions of the liners within the support contact openings.
• Formation of fill material within the slots and contact openings to create sacrificial slot structures, sacrificial contact structures, and support contact structures.
• Replacement of sacrificial contact structures with conductive contact structures.
• Removal of sacrificial slot structures.
• Replacement of sacrificial material in the tiers with conductive material.

Potential applications of this technology:

• Microelectronic devices manufacturing.
• Integrated circuits fabrication.
• Semiconductor device production.

Problems solved by this technology:

• Provides a method for forming microelectronic devices with improved contact structures.
• Enables the creation of sacrificial slot structures for precise device fabrication.
• Allows for the replacement of sacrificial materials with conductive materials.

Benefits of this technology:

• Enhanced performance and functionality of microelectronic devices.
• Improved electrical contact between different layers of the device.
• Enables the creation of complex and precise structures within the device.
• Facilitates the production of high-quality integrated circuits.

Abstract

Methods of forming a microelectronic device includes forming a preliminary stack structure including blocks separated by slots, each block including: tiers each including insulative material and sacrificial material; and live contact openings and support contact openings extending completely through the tiers. A first liner and a second liner are formed over surfaces of the preliminary stack structure. Portions of the second liner and the first liner within the support contact openings are removed without removing additional portions of the second liner and the first liner within the slots and the live contact openings. Fill material is formed within the slots, the live contact openings, and the support contact openings to form sacrificial slot structures, sacrificial contact structures, and support contact structures. The sacrificial contact structures are replaced with conductive contact structures. The sacrificial slot structures are removed, and the sacrificial material of the tiers is replaced with conductive material.

PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE (17860021)

Main Inventor

Shruti Jain

Brief explanation

The patent application describes a 3D memory device that consists of a stack of supporting lattice layers and dielectric layers on a substrate. The device includes memory pillars that vertically penetrate the stack and are made up of vertically connected replacement gate (RG) memory cells. Additionally, there are supporting buttress (SBT) pillars located at the outside ends of the memory pillars that vertically penetrate the stack. The memory pillars and SBT pillars are laterally connected by the supporting lattice layers.

• The memory device is three-dimensional and includes a stack of supporting lattice layers and dielectric layers.
• Memory pillars are present in the device and vertically penetrate the stack.
• The memory pillars consist of vertically connected replacement gate (RG) memory cells.
• The memory pillars have a square shape in a horizontal plane parallel to the supporting lattice layers.
• Supporting buttress (SBT) pillars are located at the outside ends of the memory pillars and also vertically penetrate the stack.
• The memory pillars and SBT pillars are laterally connected by the supporting lattice layers.

Potential Applications

• This 3D memory device can be used in various electronic devices such as computers, smartphones, and tablets.
• It can be utilized in data storage systems, allowing for increased memory capacity in a smaller form factor.
• The device can be integrated into artificial intelligence systems, enabling faster and more efficient data processing.

Problems Solved

• The 3D memory device solves the problem of limited memory capacity in electronic devices by utilizing a vertical stacking approach.
• It addresses the need for smaller and more compact memory solutions without compromising performance.
• The device solves the challenge of increasing data processing requirements by providing a higher density of memory cells.

Benefits

• The 3D memory device offers increased memory capacity compared to traditional two-dimensional memory structures.
• It allows for a smaller form factor, enabling the development of more compact and portable electronic devices.
• The device provides faster data processing and improved performance due to the vertically connected memory cells.

Abstract

A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first square peripheral shape in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH THREE STRIPE TECHNIQUE (17860027)

Main Inventor

Anton P. Eppich

Brief explanation

The patent application describes a 3D memory device that consists of a stack of supporting lattice layers and dielectric layers on a substrate. The device includes memory pillars that vertically penetrate the stack and are made up of vertically connected replacement gate (RG) memory cells. The memory pillars have a polygon shape with at least six sides in a horizontal plane parallel to the supporting lattice layers. Additionally, there are supporting buttress (SBT) pillars located at the outside ends of the memory pillars that vertically penetrate the stack. The memory pillars and SBT pillars are connected laterally by the supporting lattice layers.

• The 3D memory device consists of a stack of supporting lattice layers and dielectric layers on a substrate.
• Memory pillars, made up of vertically connected RG memory cells, vertically penetrate the stack.
• Memory pillars have a polygon shape with at least six sides in a horizontal plane parallel to the supporting lattice layers.
• Supporting buttress (SBT) pillars, exclusive of any memory cells, are located at the outside ends of the memory pillars and vertically penetrate the stack.
• The memory pillars and SBT pillars are laterally connected by the supporting lattice layers.

Potential Applications

• High-density memory storage devices
• Data centers and cloud computing infrastructure
• Mobile devices and smartphones
• Artificial intelligence and machine learning systems

Problems Solved

• Increased memory density and storage capacity
• Improved performance and speed of memory devices
• Enhanced reliability and durability of memory cells
• Efficient use of space in memory devices

Benefits

• Higher memory density allows for more data storage in a smaller footprint
• Faster data access and retrieval due to improved performance
• Increased reliability and durability of memory cells
• Optimal utilization of space in memory devices

Abstract

A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape having at least six sides in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

MODULAR CONSTRUCTION OF HYBRID-BONDED SEMICONDUCTOR DIE ASSEMBLIES AND RELATED SYSTEMS AND METHODS (17830224)

Main Inventor

Bharat Bhushan

Brief explanation

The abstract describes a patent application for stacked semiconductor assemblies, which involve multiple modules stacked on top of each other. Each module consists of a base die and one or more upper dies, with hybrid bonds connecting the dies together. The lowermost module is also connected to a lowermost die through hybrid bonds. The sizes of the dies decrease as you move up the stack.

• Stacked semiconductor assemblies with multiple modules
• Each module consists of a base die and one or more upper dies
• Hybrid bonds are used to connect the dies within each module
• Hybrid bonds also connect the lowermost module to the lowermost die
• Sizes of the dies decrease as you move up the stack

Potential Applications

• High-performance computing systems
• Data centers
• Artificial intelligence applications
• Internet of Things devices
• Mobile devices

Problems Solved

• Efficient use of space in semiconductor assemblies
• Improved performance and functionality in stacked modules
• Enhanced connectivity between dies within each module

Benefits

• Increased computing power and speed
• Reduced footprint and size of semiconductor assemblies
• Improved thermal management
• Enhanced scalability and flexibility in system design

Abstract

Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE (17887362)

Main Inventor

Vijayakrishna J. Vankayala

Brief explanation

The patent application describes techniques for reducing inter-die signal loads within a multi-die package. The package includes a first memory die and at least one second memory die connected via an inter-die connection. The technique involves adding an additional wirebond pad to each die in the package. When making the inter-die connections, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. This allows the first memory die to transmit inter-die signals to the second memory die with a lower signal load within the multi-die package.

• Additional wirebond pads are added to each die in a multi-die package.
• The wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die.
• This reduces inter-die signal loads within the multi-die package.

Potential Applications

• Multi-die packages in electronic devices such as smartphones, tablets, and computers.
• Memory modules in data centers and servers.

Problems Solved

• Reduces inter-die signal loads, improving signal integrity and reducing noise within the multi-die package.
• Enables efficient communication between memory dies in a multi-die package.

Benefits

• Improved performance and reliability of multi-die packages.
• Enhanced signal integrity and reduced noise.
• Cost-effective solution for reducing inter-die signal loads.

Abstract

Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.

REPEATER SCHEME FOR INTER-DIE SIGNALS IN MULTI-DIE PACKAGE (17887372)

Main Inventor

Vijayakrishna J. Vankayala

Brief explanation

The patent application describes techniques for repeating inter-die signals within a multi-die package of a memory device. 

• A multi-die package includes a memory stack with a first memory die and at least one second memory die connected via an inter-die connection.
• A multiplexer is placed in front of the transmitter of each die to repeat inter-die signals within the memory stack.
• The repetition of signals is determined based on factors like signal type, intended recipient, and stack height of the memory stack.

Potential Applications

• Memory devices in electronic devices like smartphones, tablets, and computers.
• Data centers and servers that require high-performance memory systems.

Problems Solved

• Ensures reliable communication between memory dies within a multi-die package.
• Helps overcome signal degradation and loss due to inter-die connections.
• Improves overall performance and data transfer rates in memory devices.

Benefits

• Enhanced signal integrity and reliability within the memory stack.
• Improved data transfer rates and overall performance of the memory device.
• Enables efficient communication between memory dies in a multi-die package.

Abstract

Systems, methods, and devices related to techniques for repeating inter-die signals within a multi-die package of a memory device are disclosed. The multi-die package includes a memory stack including a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communicate with the first memory die via an inter-die connection. A technique involves incorporating the use of a multiplexer positioned in front of the transmitter of each die to facilitate repetition of inter-die signals within the memory stack as needed depending on various factors associated with the memory stack, such as, but not limited to, the type of signal, the intended recipient of the inter-die signals, and the stack height of the memory stack.

SEMICONDUCTOR DEVICES HAVING ALIGNED FRONT-END INTERFACE CONTACTS AND BACK-END INTERFACE CONTACTS, AND ASSOCIATED SYSTEMS AND METHODS (18202249)

Main Inventor

Chin Hui Chong

Brief explanation

The abstract describes a patent application for semiconductor devices, specifically memory devices, and the associated systems and methods. The memory device includes a substrate with circuitry, back-end contacts, and front-end contacts. The front-end contacts receive electrical signals from an external device through a front-end interface. The front-end contacts are aligned along an axis with corresponding back-end contacts.

• The patent application is for semiconductor devices, particularly memory devices.
• The memory device includes a substrate with circuitry.
• It has back-end contacts that are electrically coupled to the circuitry.
• The device also has front-end contacts that receive electrical signals from an external device.
• The front-end contacts are aligned along an axis with corresponding back-end contacts.

Potential Applications

• Memory devices can be used in various electronic devices such as computers, smartphones, and tablets.
• The technology can be applied in data storage systems, improving their performance and efficiency.

Problems Solved

• The alignment of front-end and back-end contacts ensures efficient and accurate transmission of electrical signals.
• The patent addresses the need for reliable and high-performance memory devices.

Benefits

• The alignment of front-end and back-end contacts improves the overall performance of the memory device.
• The technology provides a more efficient and reliable data transfer between the memory device and external devices.
• The patent application introduces an innovative approach to semiconductor devices, enhancing their functionality and usability.

Abstract

Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (17833749)

Main Inventor

Takuya Imamoto

Brief explanation

The patent application describes a semiconductor device that includes two transistors of the same conductivity type. 

• The first transistor has a first gate insulating film and a first gate structure consisting of three conductive films stacked on top of each other.
• The second transistor also has a gate insulating film and a gate structure, but it consists of only two conductive films stacked on top of each other.
• The gate insulating films for both transistors are the same material.
• The second conductive film in the first transistor and the fourth conductive film in the second transistor are made of the same material.
• Similarly, the third conductive film in the first transistor and the fifth conductive film in the second transistor are made of the same material.

Potential applications of this technology:

• Integrated circuits: The semiconductor device can be used in the fabrication of integrated circuits, allowing for more efficient and compact designs.
• Electronics manufacturing: The technology can be applied in the manufacturing of various electronic devices, such as smartphones, computers, and televisions.

Problems solved by this technology:

• Simplified fabrication process: By using the same gate insulating film and the same materials for certain conductive films in both transistors, the manufacturing process can be simplified, reducing complexity and cost.
• Improved performance: The design of the semiconductor device may lead to improved performance in terms of speed, power consumption, and reliability.

Benefits of this technology:

• Cost-effective manufacturing: The simplified fabrication process can lead to cost savings in the production of semiconductor devices.
• Enhanced device performance: The design improvements may result in better overall performance of electronic devices utilizing these semiconductor devices.
• Compact and efficient designs: The technology allows for more compact and efficient designs of integrated circuits, enabling smaller and more powerful electronic devices.

Abstract

A semiconductor device includes a first transistor of a first conductivity type having a first gate insulating film and a first gate structure on the first gate insulating film, the first gate structure including a first conductive film, a second conductive film on the first conductive film and a third conductive film on the second conductive film; and a second transistor of the first conductivity type having a second gate insulating film and a second gate structure on the second gate insulating film, the second gate structure including a fourth conductive film and a fifth conductive film on the fourth conductive film; wherein the first gate insulating film and the second gate insulating film are the same, the second conductive film and the fourth conductive film are the same and the third conductive film and the fifth conductive film are the same.

DIELECTRIC ENGINEERED TUNNEL REGION IN MEMORY CELLS (17830013)

Main Inventor

Jae Young Ahn

Brief explanation

==Abstract==

The patent application describes memory devices with memory cells that have an engineered tunnel region between a channel structure and a charge storage region. The engineered tunnel region improves the read, program, and retention operations of the memory.

• The engineered tunnel region consists of multiple dielectric regions with a modulation of dielectric constant.
• The dielectric regions include materials with low and high dielectric constants relative to silicon nitride.
• Some dielectric regions have deep traps near the charge storage region.

Potential Applications

• Memory devices in various electronic devices such as smartphones, tablets, and computers.
• Data storage in cloud computing systems.
• Solid-state drives (SSDs) for faster and more reliable data storage.

Problems Solved

• Improved read, program, and retention operations of memory cells.
• Enhanced performance and reliability of memory devices.
• Increased data storage capacity and efficiency.

Benefits

• Faster and more efficient data access and retrieval.
• Higher data storage capacity.
• Improved reliability and durability of memory devices.

Abstract

A variety of applications can include memory devices having memory cells, where each memory cell can have an engineered tunnel region between a channel structure of the memory cell and a charge storage region of the memory cell. The engineered tunnel region can be directed to improved read, program, and retention operations of the memory region. In various embodiments, the engineered tunnel region can have multiple dielectric regions with a dielectric constant modulation by inserting material having a dielectric constant that is low relative to silicon nitride and material having a dielectric constant that is high relative to silicon nitride. In various embodiments, the engineered tunnel region of a memory cell can have multiple dielectric regions with material having deep traps near the charge storage region of the memory cell. Other engineered tunnel regions are disclosed.

Ferroelectric Assemblies and Methods of Forming Ferroelectric Assemblies (18235740)

Main Inventor

Albert Liao

Brief explanation

The patent application describes ferroelectric assemblies and a method of forming them. Here are the key points:

• The invention involves a capacitor with a ferroelectric insulative material between two electrodes.
• A metal oxide with a thickness of less than or equal to about 30 Å is placed between the second electrode and the ferroelectric insulative material.
• The method of forming the assembly includes the steps of:

 * Creating a first capacitor electrode on a semiconductor-containing base.
 * Applying ferroelectric insulative material over the first electrode.
 * Depositing a metal-containing material over the ferroelectric insulative material.
 * Oxidizing the metal-containing material to form a metal oxide.
 * Creating a second electrode over the metal oxide.

Potential applications of this technology:

• Memory devices: The ferroelectric assemblies can be used in non-volatile memory devices, such as ferroelectric random-access memory (FeRAM) or ferroelectric tunnel junctions (FTJ).
• Sensors: The ferroelectric assemblies can be utilized in various sensors, such as pressure sensors or temperature sensors.
• Energy storage: The capacitors with ferroelectric insulative material can be employed in energy storage devices, such as supercapacitors or batteries.

Problems solved by this technology:

• Improved performance: The use of a metal oxide layer between the ferroelectric insulative material and the second electrode enhances the performance and stability of the assembly.
• Reduced leakage current: The metal oxide layer helps to minimize leakage current, improving the efficiency of the capacitor.
• Compatibility with semiconductor technology: The method of forming the assembly is compatible with semiconductor fabrication processes, allowing for integration with other electronic components.

Benefits of this technology:

• Enhanced memory capabilities: The ferroelectric assemblies provide high-density, non-volatile memory storage with fast read and write operations.
• Improved sensor performance: The ferroelectric assemblies offer high sensitivity and accuracy in sensing applications.
• Increased energy storage capacity: The capacitors with ferroelectric insulative material provide high energy density and long cycle life in energy storage devices.

Abstract

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Integrated Circuitry, Method Used In The Fabrication Of A Vertical Transistor, And Method Used In The Fabrication Of Integrated Circuitry (18236056)

Main Inventor

Masihhur R. Laskar

Brief explanation

The abstract of the patent application describes integrated circuitry that includes an electronic component and insulative silicon dioxide adjacent to the component. The silicon dioxide has a specific concentration of elemental-form hydrogen (H) and nitrogen (N).

• The insulative silicon dioxide in the integrated circuitry has a controlled concentration of elemental-form hydrogen and nitrogen.
• The average concentration of elemental-form hydrogen is between 0.002 and 0.5 atomic percent.
• The average concentration of elemental-form nitrogen is between 0.005 and 0.3 atomic percent.

Potential Applications:

• This technology can be applied in the manufacturing of integrated circuits.
• It can be used in various electronic devices such as smartphones, computers, and microprocessors.

Problems Solved:

• The controlled concentration of elemental-form hydrogen and nitrogen helps improve the performance and reliability of integrated circuits.
• It addresses issues related to insulation and protection of electronic components in integrated circuitry.

Benefits:

• The specific concentration of hydrogen and nitrogen in the insulative silicon dioxide enhances the functionality and durability of integrated circuits.
• It improves the overall performance and efficiency of electronic devices.
• The technology provides a more reliable and stable operation of integrated circuits.

Abstract

Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

SELF-ALIGNED ETCHING TECHNIQUES FOR MEMORY FORMATION (17804997)

Main Inventor

John Hopkins

Brief explanation

The patent application describes a self-aligned etching technique for memory formation. It involves the use of a stack of alternating materials and a pillar to create multiple memory cells. A polysilicon material is formed above the pillar and is associated with a selector device for the memory cells. A masking material is then formed above the polysilicon material and the stack of alternating materials. The masking material is aligned with the polysilicon material and has a greater width than the polysilicon material and the pillar. This masking material prevents the removal of the polysilicon material, the pillar, and a portion of the stack of alternating materials during an etching operation.

• Memory device with self-aligned etching technique for memory formation
• Stack of alternating materials and a pillar form multiple memory cells
• Polysilicon material above the pillar associated with a selector device
• Masking material prevents removal of polysilicon material, pillar, and portion of stack during etching operation

Potential Applications

• Semiconductor industry
• Memory chip manufacturing
• Electronic devices

Problems Solved

• Accurate and precise etching of memory cells
• Alignment of materials during the etching process
• Prevention of unwanted removal of materials

Benefits

• Improved memory device performance
• Enhanced manufacturing efficiency
• Cost-effective production of memory chips

Abstract

Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

Integrated Assemblies and Methods of Forming Integrated Assemblies (18236265)

Main Inventor

David K. Hwang

Brief explanation

The abstract describes an integrated assembly with an upwardly-extending structure that has a sidewall surface. Two-dimensional material is present along the sidewall surface, with first and second electrostatic-doping materials adjacent to lower and upper regions of the two-dimensional material, respectively. Insulative material is present in the central region of the two-dimensional material, and a conductive gate structure is positioned over the first electrostatic-doping material and adjacent to the insulative material.

• Integrated assembly with an upwardly-extending structure and a sidewall surface
• Two-dimensional material extends along the sidewall surface
• First electrostatic-doping material is adjacent to the lower region of the two-dimensional material
• Insulative material is adjacent to the central region of the two-dimensional material
• Second electrostatic-doping material is adjacent to the upper region of the two-dimensional material
• Conductive gate structure is positioned over the first electrostatic-doping material and adjacent to the insulative material

Potential Applications

• Semiconductor devices
• Electronics manufacturing
• Nanotechnology research

Problems Solved

• Provides a structure for integrated assemblies with improved performance and functionality
• Enables precise control of electrical properties in two-dimensional materials
• Facilitates the development of advanced semiconductor devices

Benefits

• Enhanced performance and functionality of integrated assemblies
• Improved control over electrical properties in two-dimensional materials
• Enables the creation of more advanced and efficient semiconductor devices

Abstract

Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

CONROL LOOP CIRCUITRY (17892760)

Main Inventor

Steven J. Baumgartner

Brief explanation

The patent application describes apparatuses and methods for control loop circuitry, specifically an interface circuit with a digital to analog converter (DAC) that provides a differential output signal. The circuit includes two control loop portions - the first one receives a gain reference voltage and outputs a first bias voltage to the DAC, while the second one receives a common mode voltage of a differential input signal and outputs a second bias voltage to the DAC.

• The interface circuit includes a digital to analog converter (DAC) that provides a differential output signal.
• The first control loop portion receives a gain reference voltage and outputs a first bias voltage to the DAC.
• The second control loop portion receives a common mode voltage of a differential input signal and outputs a second bias voltage to the DAC.

Potential applications of this technology:

• Control loop circuitry in various electronic devices and systems.
• Signal processing applications that require precise control of bias voltages.
• Communication systems where maintaining a specific common mode voltage is crucial.

Problems solved by this technology:

• Provides a simplified and efficient way to control the bias voltages in a control loop circuit.
• Ensures accurate and stable output signals by adjusting the bias voltages based on reference voltages.
• Helps maintain the desired common mode voltage in differential input signals.

Benefits of this technology:

• Improved performance and accuracy in control loop circuitry.
• Enhanced signal processing capabilities with precise control of bias voltages.
• Increased stability and reliability in communication systems.

Abstract

Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING (17829924)

Main Inventor

Eyal En Gad

Brief explanation

Abstract:

A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

Explanation:

• A processing device in a memory system reads a sense word from a memory device.
• The processing device executes multiple parity check equations on subsets of the sense word.
• The results of the parity check equations are used to determine a syndrome for the sense word.
• The processing device checks if the syndrome satisfies a codeword criterion.
• If the syndrome does not satisfy the codeword criterion, the processing device performs an iterative LDPC correction process.
• The LDPC correction process uses a scaled bit flip threshold to correct errors in the sense word.

Potential Applications:

• Error correction in memory systems
• Data storage systems
• Communication systems

Problems Solved:

• Correcting errors in memory systems
• Improving data reliability in storage and communication systems

Benefits:

• Improved error correction capabilities
• Enhanced data integrity and reliability
• Increased system performance and efficiency

Abstract

A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

DYNAMIC DECODING FOR MEMORY SYSTEMS (17833371)

Main Inventor

Curtis W. Egan

Brief explanation

The present disclosure describes a system component, such as a memory sub-system controller, that can dynamically decode read data for zone-based memory allocations. Here is a simplified explanation of the abstract:

• The memory sub-system controller reads an entire memory block or zone.
• It decodes a first portion of the memory block or zone using a first decoding process.
• If the controller determines that a second portion of the memory block or zone satisfies a criterion, it applies a second decoding process to decode the second portion.

Potential Applications:

• This technology can be applied in various memory-intensive systems, such as computer servers, data centers, and high-performance computing systems.
• It can be used in systems that require efficient memory management and allocation, such as virtual machines and cloud computing platforms.

Problems Solved:

• Traditional memory decoding processes may be inefficient and time-consuming when dealing with large memory blocks or zones.
• This technology solves the problem of inefficient memory decoding by dynamically applying different decoding processes based on specific criteria.

Benefits:

• Improved memory decoding efficiency, as only the necessary portions of the memory block or zone are decoded.
• Faster data processing and retrieval, leading to improved system performance.
• Reduced memory access latency, resulting in faster response times for memory-intensive applications.

Abstract

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically decode read data for zone-based memory allocations. The memory sub-system controller reads an entire memory block or zone. The memory sub-system controller decodes a first portion of the memory block or zone using a first decoding process. The memory sub-system controller determines that a second portion of the memory block or zone satisfies a criterion. In response, the memory sub-system controller applies a second decoding process to decode the second portion.

EARLY STOPPING OF BIT-FLIP LOW DENSITY PARITY CHECK DECODING BASED ON SYNDROME WEIGHT (17829913)

Main Inventor

Eyal En Gad

Brief explanation

The abstract of this patent application describes a processing device in a memory system that determines the weight of a syndrome for a sense word read from a memory device. It then checks if the syndrome weight meets a certain threshold criterion. If it does, the device bypasses the first decoding operation and initiates a second decoding operation for the sense word, which has a higher error correction capability.

• The processing device in a memory sub-system determines the syndrome weight for a sense word read from a memory device.
• It checks if the syndrome weight satisfies a threshold criterion.
• If the threshold criterion is met, the device skips the first decoding operation and starts a second decoding operation for the sense word.
• The second decoding operation has a higher error correction capability than the first decoding operation.

Potential Applications

• This technology can be applied in memory systems, such as computer memory or storage devices, to improve error correction capabilities.
• It can be used in data centers or cloud computing environments to enhance the reliability and integrity of stored data.
• The innovation can also be beneficial in embedded systems, where error correction is crucial for maintaining data integrity.

Problems Solved

• The technology addresses the problem of errors in memory systems by providing a more efficient and effective error correction mechanism.
• It solves the issue of potentially incorrect data being read from memory devices by improving the error correction capability.
• The innovation helps prevent data corruption and loss, ensuring the accuracy and reliability of stored information.

Benefits

• By bypassing the first decoding operation and initiating a second decoding operation with higher error correction capability, the technology improves the accuracy of data retrieval from memory devices.
• It enhances the reliability and integrity of stored data, reducing the risk of data corruption or loss.
• The innovation can lead to improved system performance and reduced downtime, as errors are corrected more efficiently.

Abstract

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

ERROR CORRECTION (17969856)

Main Inventor

Marco Sforzin

Brief explanation

The patent application describes a method, system, and devices for mapping pairs of bits from a memory transfer block (MTB) to linked die input/output (LDIO) lines. These LDIO lines connect a linked (LK) die to an interface (IF) die. In the event of a failure in one of the LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction is performed on the pairs of bits mapped to the failed LDIO line. Each pair of bits represents a symbol for the BCH error correction.

• The patent application focuses on mapping pairs of bits from a memory transfer block (MTB) to linked die input/output (LDIO) lines.
• These LDIO lines connect a linked (LK) die to an interface (IF) die.
• In case of a failure in one of the LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction is performed on the pairs of bits mapped to the failed LDIO line.
• Each pair of bits represents a symbol for the BCH error correction.

Potential Applications

This technology has potential applications in various fields, including:

• Semiconductor industry
• Memory systems
• Data storage devices
• Communication systems

Problems Solved

The patent application addresses the following problems:

• Failure of LDIO lines in the communication between linked die and interface die
• Ensuring reliable data transfer between the linked die and interface die
• Correcting errors in the transferred data caused by LDIO line failures

Benefits

The technology described in the patent application offers several benefits, such as:

• Improved reliability of data transfer
• Efficient error correction using Bose-Chaudhuri-Hocquenghem (BCH) codes
• Enhanced performance and functionality of memory systems and communication devices
• Increased data integrity and accuracy

Abstract

Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.

ERROR REDUCTION DURING CRYPTOGRAPHIC KEY UPDATES IN SECURE MEMORY DEVICES (17831364)

Main Inventor

Zhan Liu

Brief explanation

The patent application describes a system for securely delivering cryptographic keys to memory devices. The system includes a memory device with a key storage area, a key management server (KMS), and a manufacturer computing device.

• The KMS receives a key request and generates a cryptographic key.
• The KMS computes a hash of the cryptographic key and returns both the key and the hash in response to the request.
• The manufacturer computing device receives the key and hash and sends a command to the memory device.
• The memory device computes a local hash using the key in the command.
• The memory device compares the local hash to the received hash.
• If the local hash matches the received hash, the memory device writes the cryptographic key to the key storage area.

Potential applications of this technology:

• Secure delivery of cryptographic keys to memory devices.
• Enhancing the security of memory devices by ensuring the integrity of the received keys.

Problems solved by this technology:

• Ensuring the secure delivery of cryptographic keys to memory devices.
• Verifying the integrity of the received keys.

Benefits of this technology:

• Improved security for memory devices.
• Protection against unauthorized access to cryptographic keys.
• Simplified and efficient key delivery process.

Abstract

The disclosure relates to improvements in key delivery to secure memory devices. In some implementations, the techniques described herein relate to a system including: a memory device including a key storage area; a key management server (KMS) configured to receive a key request, generate a cryptographic key, compute a hash of the cryptographic key, and return the cryptographic key and the hash in response to the key request; and a manufacturer computing device configured to receive the cryptographic key and the hash as part of the response to the key request and issue a command including the cryptographic key and the hash to the memory device, wherein the memory device is configured to compute a local hash using the cryptographic key in the command, compare the local hash to the hash, and write the cryptographic key to the key storage area when the local hash matches the hash.

DEVICE IDENTIFIER COMPOSITION ENGINE 3-LAYER ARCHITECTURE (17810952)

Main Inventor

Alessandro ORLANDO

Brief explanation

The abstract describes a device identifier composition engine (DICE) architecture for secure computing environments. The architecture includes three layers: DICE layer 0, DICE layer 1, and a controller. 

• The DICE layer 0 component derives a DICE identity key.
• The DICE layer 1 component derives a DICE alias key based on the DICE identity key.
• The controller receives firmware updates for components and updates the firmware accordingly.
• The controller can also update the keys of the component or other components in the layer stack.

Potential applications of this technology:

• Secure computing environments in devices such as smartphones, tablets, or IoT devices.
• Authentication and identification systems for secure access control.
• Protection against unauthorized access and tampering of firmware and keys.

Problems solved by this technology:

• Ensures the security and integrity of firmware and keys in a device.
• Provides a secure computing environment with a hardware root of trust.
• Enables secure communication and authentication between devices.

Benefits of this technology:

• Enhanced security and protection against unauthorized access and tampering.
• Simplified and efficient management of firmware updates and key updates.
• Enables secure and reliable identification and authentication of devices.

Abstract

Implementations described herein relate to a device identifier composition engine (DICE) 3-layer architecture. In some implementations, a device may include a secure computing environment including a hardware root of trust (HRoT) DICE component. The secure computing environment may include a DICE layer 0 component configured to derive a DICE identity key. The secure computing environment may include a DICE layer 1 component configured to derive a DICE alias key based on the DICE identity key. The secure computing environment may include a controller configured to receive an update to firmware of a component. The controller may be configured to update the firmware of the component based on receiving the update. The controller may be configured to update one or more keys of the component or one or more keys of one or more components above the component in a layer stack.

METHODS TO SECURE ACCESS TO AN AUTOMOBILE AND AN AUTHENTICATED IGNITION SYSTEM (17831353)

Main Inventor

Sourin Sarkar

Brief explanation

The patent application describes a method for enabling access and ignition of a vehicle using a wireless transceiver and biometric data of a legitimate user. Here is a simplified explanation of the abstract:

• A wireless transceiver installed in a vehicle receives a radio signal.
• The method determines if the radio signal is generated by a legitimate user by analyzing the biometric data of the user and a unique device identifier (UDI) included in the radio signal.
• If the radio signal is determined to be from a legitimate user, access to the vehicle is enabled.
• Additionally, the method enables ignition of the vehicle based on the biometric data and the UDI.

Potential Applications

This technology can have various applications in the automotive industry and beyond. Some potential applications include:

• Vehicle security systems: The method can enhance the security of vehicles by ensuring that only authorized users can access and start the vehicle.
• Car rental services: Rental companies can use this technology to streamline the process of renting vehicles, allowing customers to access and start the rented vehicle using their biometric data.
• Fleet management: Companies with vehicle fleets can use this method to monitor and control access to their vehicles, ensuring that only authorized drivers can operate them.

Problems Solved

The technology addresses several problems in vehicle access and security:

• Unauthorized access: By utilizing biometric data and a unique device identifier, the method ensures that only legitimate users can access and start the vehicle, reducing the risk of theft or unauthorized use.
• Keyless entry vulnerabilities: Traditional keyless entry systems can be vulnerable to hacking or signal interception. This method adds an additional layer of security by verifying the legitimacy of the user through biometric data.
• Identity theft: By using biometric data, the method reduces the risk of identity theft, as it is much more difficult for someone to replicate another person's unique biometric characteristics.

Benefits

The technology offers several benefits:

• Enhanced security: By combining biometric data and a unique device identifier, the method provides a robust security system for vehicles, reducing the risk of unauthorized access and theft.
• Convenience: Users can access and start the vehicle without the need for physical keys or key fobs, making the process more convenient and eliminating the risk of losing or misplacing keys.
• Personalization: The method can be customized to recognize multiple legitimate users, allowing for personalized vehicle settings and preferences for each user.

Abstract

In some aspects, the techniques described herein relate to a method including: receiving a radio signal by a wireless transceiver installed in a vehicle; determining that the radio signal was generated by and received from a legitimate user based on a biometric data of the legitimate user and a unique device identifier (UDI) included in the radio signal; enabling access to the vehicle; and enabling ignition of the vehicle based on the biometric data and the UDI.

APPARATUS INCLUDING THERMAL MANAGEMENT MECHANISM AND METHODS OF MANUFACTURING THE SAME (18236146)

Main Inventor

Suresh Reddy Yarragunta

Brief explanation

The patent application describes an apparatus that includes a heat sink with parallel fins, which create channels for directing the flow of air or coolant across the heat sink. The channels have varying widths, wider near the inlet and narrower near the outlet.

• The apparatus includes a heat sink with parallel fins.
• The fins create colinear channels for directing the flow of air or coolant.
• The channels have wider widths closer to the inlet and narrower widths closer to the outlet.
• The purpose is to optimize the flow of air or coolant across the heat sink.

Potential Applications

This technology could be applied in various industries and systems where efficient cooling is required, such as:

• Electronics and computer systems
• Automotive cooling systems
• Industrial machinery and equipment
• Power generation and distribution systems

Problems Solved

The innovation addresses the following problems:

• Inefficient cooling due to uneven distribution of air or coolant flow across the heat sink.
• Heat sink performance limitations caused by inadequate heat dissipation.
• Overheating issues in electronic devices and systems.

Benefits

The technology offers several benefits:

• Improved cooling efficiency by optimizing the flow of air or coolant across the heat sink.
• Enhanced heat dissipation capabilities, leading to better performance and reliability.
• Reduction in overheating-related problems, extending the lifespan of electronic devices and systems.

Abstract

An apparatus including a heat sink having two or more sections of parallel fins that define colinear channels is disclosed herein. The colinear channels are configured to direct flow of air or coolant across the heat sink and have wider channel widths closer to an inlet for the air or coolant and narrower widths closer to an outlet for the air or coolant.

MULTIPLE, ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN VERTICAL THREE DIMENSIONAL (3D) MEMORY (17888460)

Main Inventor

David K. Hwang

Brief explanation

The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes formed in tiers. The system uses alternating layers of silicon germanium (SiGe) and single crystalline silicon (Si) to form the tiers.

• The memory cells are arranged in a vertical three-dimensional (3D) structure.
• The access devices have horizontally oriented first and second source/drain regions separated by a single crystalline silicon channel region.
• Gate all around (GAA) structures connect to horizontally oriented access lines opposing the channel regions.
• Vertical digit lines are coupled to the first source/drain regions.

Potential applications of this technology:

• Memory devices in computers, smartphones, and other electronic devices.
• Data storage in cloud computing and data centers.
• High-performance computing systems.

Problems solved by this technology:

• Increased memory density and capacity in a smaller footprint.
• Improved performance and speed of memory access.
• Enhanced reliability and durability of memory cells.

Benefits of this technology:

• Higher memory density allows for more data storage in a smaller space.
• Faster access to stored data improves overall system performance.
• Improved reliability ensures data integrity and reduces the risk of data loss.

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON (17888467)

Main Inventor

Si-Woo Lee

Brief explanation

The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes. The access devices have two source/drain regions separated by single crystalline silicon channel regions. A support structure is provided for the single crystalline silicon. Access lines connect to gates surrounding the channel regions, forming gate all around (GAA) structures. The memory cells have storage nodes connected to one source/drain region and vertical digit lines connected to the other source/drain region.

• The patent application describes a system for vertically stacked memory cells.
• The access devices in the system have horizontally oriented structures.
• The access devices have two source/drain regions separated by single crystalline silicon channel regions.
• A support structure is provided for the single crystalline silicon.
• Access lines connect to gates surrounding the channel regions, forming gate all around (GAA) structures.
• The memory cells in the system have storage nodes connected to one source/drain region.
• The memory cells also have vertical digit lines connected to the other source/drain region.

Potential Applications

This technology could be applied in various memory storage devices, such as:

• Solid-state drives (SSDs)
• Random-access memory (RAM)
• Flash memory

Problems Solved

The technology addresses the following problems:

• Efficiently stacking memory cells in a vertical arrangement
• Providing horizontally oriented access devices for improved performance
• Ensuring single crystalline silicon channel regions for better conductivity

Benefits

The technology offers the following benefits:

• Increased memory storage capacity due to vertical stacking
• Improved performance with horizontally oriented access devices
• Enhanced conductivity with single crystalline silicon channel regions

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

MULTIPLE, ALTERNATING EPITAXIAL SILICON (17888472)

Main Inventor

John F. Kaeding

Brief explanation

The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes. The access devices have two source/drain regions separated by a single crystalline silicon channel region. The access lines connect to gates surrounding the channel region, forming gate all around (GAA) structures. Vertical digit lines are connected to the source/drain regions.

• The patent application proposes a new design for vertically stacked memory cells.
• The access devices have horizontally oriented structures with two source/drain regions and a single crystalline silicon channel region.
• The access lines are connected to gates that surround the channel region, forming gate all around (GAA) structures.
• Vertical digit lines are connected to the source/drain regions of the access devices.

Potential applications of this technology:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage in cloud computing and data centers.
• High-performance computing systems.

Problems solved by this technology:

• The design allows for vertically stacked memory cells, increasing the storage capacity in a smaller footprint.
• The horizontally oriented access devices provide efficient access to the storage nodes.
• The gate all around (GAA) structures improve the performance and reliability of the memory cells.

Benefits of this technology:

• Increased storage capacity in a smaller footprint.
• Improved performance and reliability of the memory cells.
• Efficient access to the storage nodes.

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source/drain regions.

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17805201)

Main Inventor

Fatma Arzum Simsek-Ege

Brief explanation

The abstract describes a microelectronic device that consists of vertical stacks of memory cells, access devices, capacitors, and a conductive pillar structure. It also includes multiplexers, additional transistors, and global digit lines. The abstract mentions related electronic systems and methods.

• The microelectronic device comprises vertical stacks of memory cells.
• Each vertical stack of memory cells includes a vertical stack of access devices.
• The vertical stack of access devices is horizontally neighboring a vertical stack of capacitors.
• A conductive pillar structure vertically extends through the vertical stack of access devices.
• The microelectronic device includes multiplexers and additional transistors that are vertically overlying the vertical stacks of memory cells.
• Global digit lines are vertically overlying the multiplexer and the additional transistor.

Potential Applications

• Memory devices in electronic devices such as smartphones, computers, and tablets.
• Data storage systems in cloud computing and data centers.
• High-performance computing systems.

Problems Solved

• Efficient and compact memory storage.
• Improved data access and retrieval speed.
• Enhanced performance and reliability of electronic devices.

Benefits

• Higher memory capacity in a smaller form factor.
• Faster data processing and retrieval.
• Improved overall performance and efficiency of electronic systems.

Abstract

A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.

MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS (17830145)

Main Inventor

Sheyang Ning

Brief explanation

Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described in this patent application. The memory device includes a memory array with multiple levels of memory cells, each separated by a dielectric layer. Each memory cell at a first level includes a channel portion and a capacitor to store its logic state. The capacitor has a first portion located between the channel portion and a voltage source, and a second portion in a cavity in a dielectric layer between the first and second levels of the memory array. The second portion of the capacitor is located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

• Memory device with multiple levels of memory cells
• Capacitor structure to store logic state of memory cells
• First portion of capacitor located between channel portion and voltage source
• Second portion of capacitor in a cavity in a dielectric layer between levels
• Second portion of capacitor located between channel portion and word line of second memory cell

Potential Applications

• Three-dimensional memory arrays
• High-density memory devices
• Data storage in electronic devices

Problems Solved

• Increasing memory density in limited space
• Efficient storage of logic states in memory cells
• Reducing interference between memory cells

Benefits

• Higher memory capacity in smaller footprint
• Improved performance and reliability of memory devices
• Enhanced data storage capabilities in electronic devices

Abstract

Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

MICROELECTRONIC DEVICES, AND RELATED METHODS OF FORMING MICROELECTRONIC DEVICES (18054316)

Main Inventor

Si-Woo Lee

Brief explanation

The abstract describes a microelectronic device that consists of vertical stacks of memory cells. Each stack includes access devices, capacitors, and a conductive pillar structure. Transistor structures are placed above the memory cells, with a protective liner material in between. The abstract also mentions related methods.

• The microelectronic device has vertical stacks of memory cells.
• Each stack includes access devices, capacitors, and a conductive pillar structure.
• Transistor structures are placed above the memory cells.
• A protective liner material is used to separate the semiconductive material and the conductive pillar structure.
• The abstract also mentions related methods.

Potential Applications

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage in servers and data centers.
• High-performance computing systems.

Problems Solved

• Efficient memory storage and access in microelectronic devices.
• Protection of the semiconductive material from the conductive pillar structure.
• Integration of access devices, capacitors, and transistor structures in a vertical stack.

Benefits

• Increased memory capacity and performance.
• Enhanced reliability and durability of the microelectronic device.
• Improved integration and compactness of memory cells.

Abstract

A microelectronic device comprises vertical stacks of memory cells, each of the vertical stacks of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in contact with the vertical stack of access devices. The microelectronic device further comprises transistor structures vertically overlying the vertical stacks of memory cells and comprising semiconductive material, and a protective liner material horizontally intervening between the semiconductive material and the conductive pillar structure of each of the vertical stacks of memory cells. Related methods are also described.

APPARATUSES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17813420)

Main Inventor

Mitsunari Sukekawa

Brief explanation

The abstract describes an apparatus that includes semiconductive pillar structures, each consisting of a digit line contact region between two storage node contact regions. One of the semiconductive pillar structures has a first end portion with a first storage node contact region, a second end portion with a second storage node contact region, and a central portion with the digit line contact region. There are also two intervening portions between the end portions and the central portion, with each having a different orientation than the central portion.

• The apparatus includes semiconductive pillar structures with specific regions for digit line and storage node contacts.
• One of the semiconductive pillar structures has a unique design with angled intervening portions.
• The angled intervening portions have a different orientation than the central portion.
• The apparatus can be used in memory devices and electronic systems.
• The invention also includes methods of forming the apparatus.

Potential Applications

• Memory devices
• Electronic systems

Problems Solved

• Efficient contact arrangement in semiconductive pillar structures
• Improved performance and functionality of memory devices

Benefits

• Enhanced memory device performance
• Increased storage capacity
• Improved reliability and durability

Abstract

An apparatus comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, a central portion between the first end portion and the second end portion and comprising the digit line contact region, a first intervening portion between the first end portion and the central portion, and a second intervening portion between the second end portion and the central portion. A longitudinal axis of each of the first intervening portion and the second intervening portion is oriented at an angle with respect to a longitudinal axis of the central portion. Related memory devices, electronic systems, and methods of forming the apparatus are also described.

MICROELECTRONIC DEVICES INCLUDING IMPLANT REGIONS, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (17805167)

Main Inventor

Zhiqiang Teo

Brief explanation

The patent application describes a microelectronic device that includes various structures and materials to improve its performance and functionality. 

• The device includes lateral contact structures made of conductive material, which are positioned over a source structure.
• A cap material is placed over the lateral contact structures and contains implant regions with implant regions.
• A stack structure is then added on top of the cap material, consisting of alternating layers of insulative and conductive structures arranged in tiers.
• Pillars are vertically extended through the stack structure and into the source structure, with each pillar having semiconductive channel material in contact with the lateral contact structures.
• The device also includes filled slot structures that extend vertically through the stack structure and cap material, positioned within the implant regions of the cap material.

Potential applications of this technology:

• Memory devices: The microelectronic device described in the patent application can be used in memory devices to improve their performance and functionality.
• Electronic systems: The technology can be applied in various electronic systems, such as computers, smartphones, and IoT devices, to enhance their capabilities.

Problems solved by this technology:

• Improved performance: The use of lateral contact structures, cap material with implant regions, and stack structure helps to enhance the performance of the microelectronic device.
• Increased functionality: The addition of filled slot structures within the implant regions allows for additional functionality and improved integration within electronic systems.

Benefits of this technology:

• Enhanced performance: The various structures and materials used in the microelectronic device contribute to improved performance, such as faster data processing and higher efficiency.
• Increased functionality: The addition of filled slot structures provides additional functionality and flexibility in the design and integration of the device into electronic systems.
• Improved integration: The design of the device allows for better integration within electronic systems, enabling seamless connectivity and compatibility.

Abstract

A microelectronic device comprises lateral contact structures overlying a source structure and comprising conductive material, a cap material overlying the lateral contact structures and comprising implant regions therein, a stack structure overlying the cap material and comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers, and pillars vertically extending through the stack structure and into the source structure. The pillars individually comprise semiconductive channel material in physical contact with the lateral contact structures. The microelectronic device comprises filled slot structures vertically extending at least through the stack structure and the cap material. The filled slot structures are positioned within horizontal areas of the implant regions of the cap material. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

VERTICAL NON-VOLATILE MEMORY WITH LOW RESISTANCE SOURCE CONTACT (17816651)

Main Inventor

Darwin A. Clampitt

Brief explanation

The abstract describes a system for manufacturing a memory device by forming a trench between two portions of a stack. The trench has a bottom wall made of a spacer material. The system removes certain materials to reform the trench and expose a third oxide material and a channel structure. The system then removes more materials from the channel structure and deposits a metal material in the trench, in contact with a doped polysilicon material of the channel structure.

• The system forms a trench between two portions of a stack in a memory device.
• The trench has a bottom wall made of a spacer material.
• Certain oxide materials are removed to reform the trench.
• Polysilicon material is removed in a lateral direction to expose a third oxide material and a channel structure.
• More oxide materials are removed from the channel structure.
• A metal material is deposited in the trench, in contact with a doped polysilicon material of the channel structure.

Potential Applications

• Manufacturing memory devices
• Semiconductor industry

Problems Solved

• Efficient formation of trenches in memory devices
• Proper exposure of oxide materials and channel structures
• Effective deposition of metal material in the trench

Benefits

• Improved manufacturing process for memory devices
• Enhanced performance and functionality of memory devices
• Cost-effective production of memory devices

Abstract

For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17830108)

Main Inventor

John D. Hopkins

Brief explanation

The abstract describes a method for forming a memory array using memory cells. Here are the key points:

• The method involves creating a conductor tier on a substrate.
• Memory-block regions are formed above the conductor tier, consisting of alternating first and second tiers.
• Channel-material strings pass through these tiers.
• Conducting material is formed in the lower first tier, connecting the channel material and the conductor material.
• The conducting material has an upper portion, a lower portion, and a void-space in between.
• Silicon is selectively deposited into the void-space, onto and from the exposed silicon-containing surface.

Potential applications of this technology:

• Memory arrays in electronic devices
• Data storage systems
• Computer memory modules

Problems solved by this technology:

• Efficient formation of memory arrays
• Improved connectivity between memory cells and conductor material

Benefits of this technology:

• Higher memory density
• Faster data transfer
• Enhanced reliability and durability of memory arrays

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.

MEMORY DEVICE INCLUDING PREFORMED RECESSES BETWEEN CONTACT STRUCTURES AND CONTROL GATES (17876271)

Main Inventor

Mallesh Rajashekharaiah

Brief explanation

The abstract describes an apparatus and method for forming memory cells in a device. The apparatus includes tiers with conductive materials forming control gates for the memory cells. A staircase structure is formed in the tiers, with the conductive materials forming part of the structure. A dielectric liner is formed on the sidewall of the staircase structure, with recesses in the tiers adjacent to the sidewall. A contact structure extends through the dielectric liner, with the liner located between the contact structure and the conductive materials.

• Tiers with conductive materials form control gates for memory cells
• Staircase structure formed in the tiers, with conductive materials forming part of the structure
• Dielectric liner formed on the sidewall of the staircase structure
• Recesses in the tiers adjacent to the sidewall for the dielectric liner
• Contact structure extends through the dielectric liner, with the liner located between the contact structure and the conductive materials

Potential Applications

• Memory cell formation in electronic devices
• Semiconductor manufacturing

Problems Solved

• Efficient formation of memory cells
• Improved control gate structure

Benefits

• Enhanced memory cell performance
• Increased device functionality
• Improved manufacturing process efficiency

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including conductive materials that form part of respective control gates for memory cells of the apparatus; a staircase structure formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure; a dielectric liner formed on the sidewall; recesses formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses; and a contact structure extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are between the contract structure and the conductive materials.

MERGED CAVITIES AND BURIED ETCH STOPS FOR THREE-DIMENSIONAL MEMORY ARRAYS (17884299)

Main Inventor

Yoshiaki Fukuzumi

Brief explanation

Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described in this patent application. The invention involves forming a row of cavities using a cavity etching process and then removing the material separating the cavities to merge them and form a trench. The trench can be formed from multiple rows of cavities or a pattern of cavities with different quantities of rows at different locations along the trench. Etch stopping material portions, known as etch stops, can be formed at locations corresponding to the cavities prior to the cavity etching process by oxidizing exposed material surfaces.

• A row of cavities is formed using a cavity etching process.
• The material separating the cavities is removed to merge them and form a trench.
• The trench can be formed from multiple rows of cavities or a pattern of cavities with different quantities of rows at different locations.
• Etch stops are formed at locations corresponding to the cavities by oxidizing exposed material surfaces.

Potential Applications

• Three-dimensional memory arrays
• Semiconductor manufacturing

Problems Solved

• Efficient formation of trenches in three-dimensional memory arrays
• Improved control over the cavity etching process

Benefits

• Enhanced memory array performance
• Increased manufacturing efficiency
• Improved reliability and durability of memory devices

Abstract

Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18307698)

Main Inventor

Pengyuan Zheng

Brief explanation

The abstract describes a method of forming a microelectronic device that involves several steps including the formation of conductive interconnect structures, metal silicide material, and a dielectric material. Openings are then formed and filled with additional isolation material. Related devices and systems are also mentioned.

• The method involves forming conductive interconnect structures that extend vertically through isolation material.
• Metal silicide material is formed on the interconnect structures and the first isolation material.
• A conductive material is formed on the metal silicide material.
• A dielectric material is formed over the conductive material.
• Openings are formed vertically through the dielectric material, conductive material, metal silicide material, and isolation material.
• Additional isolation material is formed to fill the openings partially and extend over remaining portions of the dielectric material.

Potential Applications

This technology can be applied in various microelectronic devices, such as integrated circuits, microprocessors, and memory devices.

Problems Solved

The method described in the patent application solves the problem of forming conductive interconnect structures and filling openings in a microelectronic device, ensuring proper electrical connections and isolation.

Benefits

The use of metal silicide material and additional isolation material improves the conductivity and isolation properties of the microelectronic device. The vertical extension of conductive interconnect structures allows for efficient use of space in the device. The method provides a reliable and efficient way of forming microelectronic devices.

Abstract

A method of forming a microelectronic device includes forming conductive interconnect structures vertically extending through isolation material to conductive contact structures coupled to pillar structures, forming a metal silicide material on the interconnect structures and the first isolation material, forming a conductive material on the metal silicide material, and forming a dielectric material over the conductive material. The method further includes forming openings vertically extending through the dielectric material, the conductive material, the metal silicide material, and the isolation material and forming additional isolation material to extend over remaining portions of the dielectric material and at least partially fill the openings. Related devices and systems are disclosed.

MICROELECTRONIC DEVICES COMPRISING A BORON-CONTAINING MATERIAL, AND RELATED ELECTRONIC SYSTEMS AND METHODS (18324084)

Main Inventor

Jordan D. Greenlee

Brief explanation

The patent application describes a microelectronic device that includes a stack structure, a memory pillar, and a boron-containing material. The stack structure consists of alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and creates memory cells where it intersects with the conductive structures. The boron-containing material is present on at least a portion of the conductive structures.

• The microelectronic device has a stack structure with alternating conductive and dielectric structures.
• A memory pillar is present, extending through the stack structure.
• Memory cells are formed at the intersections of the memory pillar and the conductive structures.
• The conductive structures of the stack structure are coated with a boron-containing material.

Potential applications of this technology:

• Memory devices in microelectronics
• Integrated circuits
• Semiconductor devices

Problems solved by this technology:

• Enhances the performance and functionality of memory devices
• Improves the reliability and durability of microelectronic devices

Benefits of this technology:

• Increased memory capacity and speed
• Improved data storage and retrieval
• Enhanced overall performance of microelectronic devices

Abstract

A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.

FERROELECTRIC MEMORY ARRAYS WITH LOW PERMITTIVITY DIELECTRIC BARRIERS (18203886)

Main Inventor

Giorgio Servalli

Brief explanation

The patent application describes methods, systems, and devices for ferroelectric memory arrays with low permittivity dielectric barriers. These memory arrays are manufactured using a process that involves depositing a dielectric barrier between adjacent memory cells.

• The manufacturing process includes depositing a film of dielectric material over rows of bottom electrodes formed on dielectric walls, filling the space between adjacent bottom electrodes.
• Alternatively, the process involves depositing a film of dielectric material into cavities of the memory array, where each cavity has bottom electrodes formed on its sidewalls.
• After deposition, a portion of the dielectric material is removed to expose the surfaces of the bottom electrodes, leaving behind dielectric barriers between adjacent bottom electrodes.

Potential Applications

This technology can be applied in various fields, including:

• Memory devices: The ferroelectric memory arrays with low permittivity dielectric barriers can be used in various memory devices, such as computer systems, smartphones, and other electronic devices.
• Data storage: The improved memory arrays can enhance data storage capabilities, allowing for faster and more efficient data access and retrieval.
• Integrated circuits: The technology can be integrated into various integrated circuits, enabling higher performance and improved functionality.

Problems Solved

The patent application addresses several problems in the field of ferroelectric memory arrays:

• Permittivity issues: The use of low permittivity dielectric barriers helps to reduce the permittivity mismatch between the ferroelectric material and the dielectric material, improving the overall performance of the memory arrays.
• Manufacturing challenges: The described manufacturing process provides a solution for depositing and removing dielectric material to create the desired dielectric barriers between adjacent bottom electrodes.
• Memory cell interference: The dielectric barriers help to minimize interference between adjacent memory cells, improving the reliability and stability of the memory arrays.

Benefits

The technology offers several benefits:

• Improved performance: The use of low permittivity dielectric barriers enhances the performance of ferroelectric memory arrays, resulting in faster and more efficient data storage and retrieval.
• Enhanced reliability: The dielectric barriers reduce interference between memory cells, improving the reliability and stability of the memory arrays.
• Manufacturing efficiency: The described manufacturing process provides an efficient and effective way to deposit and remove dielectric material, simplifying the production of the memory arrays.

Abstract

Methods, systems, and devices for ferroelectric memory arrays with low permittivity dielectric barriers are described. In some cases, a manufacturing process to manufacture a memory array may include depositing a dielectric barrier between respective bottom electrodes of a pair of adjacent memory cells of the array. For example, the manufacturing process may include depositing a film of dielectric material over rows of bottom electrodes formed on a set of dielectric walls to at least partially fill space between adjacent bottom electrodes. Alternatively, the manufacturing process may include depositing a film of dielectric material into a set of cavities of the memory array, each cavity having a set of bottom electrodes formed on sidewalls of the cavity. Subsequently, a portion of the dielectric material may be removed to expose surfaces of the bottom electrodes, leaving behind a set of dielectric barriers between adjacent bottom electrodes.

FORMATION FOR MEMORY CELLS (18204773)

Main Inventor

Giorgio Servalli

Brief explanation

The patent application describes methods, systems, and devices for forming memory cells. Specifically, it focuses on a semiconductor device (such as a memory die) that includes asymmetrical rows of conductive pillars and one or more dielectric materials. The memory die has a set of conductive pillars arranged in rows with different spacing distances. Additionally, the memory die includes one or more dielectric materials that conformally line exposed surfaces during a self-aligning process.

• The patent application describes a semiconductor device with asymmetrical rows of conductive pillars and dielectric materials.
• The conductive pillars are arranged in rows with different spacing distances.
• The dielectric materials conformally line exposed surfaces during a self-aligning process.
• This reduces the need for subsequent masking operations in the formation of the memory die.

Potential Applications

• Memory devices
• Semiconductor manufacturing

Problems Solved

• Decreases the number of masking operations required in the formation of memory dies.
• Provides a self-aligning process for depositing dielectric materials.

Benefits

• Simplifies the formation process of memory cells.
• Reduces manufacturing time and cost.
• Improves the efficiency of memory device production.

Abstract

Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.

MEMORY DEVICE ASSEMBLY WITH A LEAKER DEVICE (17805586)

Main Inventor

Fatma Arzum SIMSEK-EGE

Brief explanation

The patent application describes various structures, integrated assemblies, and memory devices. One such memory device includes multiple memory cells with specific components and arrangements.

• Each memory cell consists of a bottom electrode in the shape of an open top cylinder, containing a support pillar.
• The memory cell also includes a top electrode and an insulator that separates the top and bottom electrodes.
• Additionally, a leaker device with an open top cylinder shape is present in the memory cell.
• The bottom surface of the leaker device abuts either the top surface of the bottom electrode or the top surface of the support pillar.
• The top surface of the leaker device abuts the bottom surface of a conductive plate.
• The memory device also includes the conductive plate.

Potential applications of this technology:

• Memory devices with improved performance and reliability.
• Enhanced data storage capabilities in electronic devices.
• Increased efficiency in data processing and retrieval.

Problems solved by this technology:

• Addressing the need for memory devices with better performance and reliability.
• Overcoming limitations in data storage capacity and speed.
• Resolving issues related to data loss or corruption.

Benefits of this technology:

• Improved memory cell design for enhanced functionality.
• Increased data storage capacity and faster data access.
• Enhanced reliability and durability of memory devices.

Abstract

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes multiple memory cells. Each memory cell may include a bottom electrode having an open top cylinder shape that contains a support pillar, may include a top electrode, may include an insulator that separates the top electrode from the bottom electrode, and may include a leaker device having an open top cylinder shape. A bottom surface of the leaker device may abut at least one of a top surface of the bottom electrode or a top surface of the support pillar. A top surface of the leaker device may abut a bottom surface of a conductive plate. The memory device may also include the conductive plate.

MEMORY DEVICE ASSEMBLY WITH REDISTRIBUTION LAYER BETWEEN TRANSISTORS AND CAPACITORS (17812233)

Main Inventor

Marcello MARIANI

Brief explanation

The patent application describes a memory device with an array of memory cells. Each memory cell consists of a transistor and a capacitor. The transistor has a pillar structure with upper and lower source/drain regions and a channel in between. The transistor also has a gate that is part of a gate line and is located near the channel. The memory cell includes a capacitor with a bottom electrode, an insulator, and a top electrode. The memory cell also includes a conductive contact region that connects the transistor and the capacitor.

• The memory device includes an array of memory cells.
• Each memory cell consists of a transistor and a capacitor.
• The transistor has a pillar structure with upper and lower source/drain regions and a channel.
• The transistor's gate is part of a gate line and is located near the channel.
• The memory cell includes a capacitor with a bottom electrode, an insulator, and a top electrode.
• The memory cell also includes a conductive contact region that connects the transistor and the capacitor.
• The conductive contact region includes the upper source/drain, a first conductive region, and a second conductive region.
• The first conductive region abuts the upper source/drain and contacts a first insulator line.
• The second conductive region abuts the upper source/drain and contacts a second insulator line parallel to the first insulator line.

Potential Applications

• Memory devices for computers, smartphones, and other electronic devices.
• Storage devices for data centers and cloud computing.
• Embedded memory in various electronic systems.

Problems Solved

• Provides a compact and efficient memory cell design.
• Enables high-density memory arrays.
• Improves the performance and reliability of memory devices.

Benefits

• Increased memory capacity in a smaller footprint.
• Faster data access and retrieval.
• Enhanced overall performance of electronic devices.
• Improved energy efficiency.

Abstract

A memory device includes an array of memory cells. A memory cell includes a transistor with a pillar that includes an upper source/drain, a lower source/drain, and a channel between the upper source/drain and the lower source/drain. The transistor includes a gate that is part of a gate line and that is proximate to the channel. The memory cell includes a capacitor having a bottom electrode, an insulator, and a top electrode. The memory cell includes a conductive contact region that couples the transistor and the capacitor and that includes the upper source/drain, a first conductive region having a right surface that abuts the upper source/drain and having a left surface that contacts a first insulator line, and a second conductive region having a left surface that abuts the upper source/drain and having a right surface that contacts a second insulator line that is parallel to the first insulator line.

MEMORY DEVICE ASSEMBLY WITH NON-IMPINGED LEAKER DEVICES (17815420)

Main Inventor

Beth R. COOK

Brief explanation

The patent application describes implementations of integrated assemblies and memory devices. 

• The integrated assembly consists of a cell plate, a top electrode, and an insulator that separates the top electrode from bottom electrodes.
• The assembly includes two groups of bottom electrodes, each coupled to the cell plate via a corresponding group of leaker devices.
• The first group of leaker devices is located in a region that includes the top electrode and the insulator.
• The second group of leaker devices is located in a region that does not include the top electrode or the insulator.
• Both groups of leaker devices have the same electrical properties.

Potential applications of this technology:

• Memory devices
• Integrated circuits
• Electronic devices requiring efficient data storage

Problems solved by this technology:

• Efficiently storing and retrieving data in memory devices
• Reducing power consumption in integrated circuits
• Improving the performance of electronic devices

Benefits of this technology:

• Improved data storage capacity
• Reduced power consumption
• Enhanced performance and reliability of electronic devices

Abstract

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a cell plate, a top electrode, and an insulator that separates the top electrode from bottom electrodes. The integrated assembly may include a first group of bottom electrodes that are coupled to the cell plate via a corresponding first group of leaker devices, wherein a first region between the first group of leaker includes the top electrode and the insulator. The integrated assembly may include a second group of bottom electrodes that are electrically coupled to the cell plate via a corresponding second group of leaker devices, wherein a second region between the second group of leaker devices does not include the top electrode and does not include the insulator. The first group of leaker devices and the second group of leaker devices have substantially identical electrical properties.

FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION (18204077)

Main Inventor

Giorgio Servalli

Brief explanation

The patent application describes a ferroelectric memory architecture that includes a gap region between memory cells to reduce capacitance between plates and eliminate undesirable coupling during memory operations. The gap region contains a fluid, such as air, with a low dielectric constant to further reduce capacitance and improve memory device speed and resource consumption.

• Memory architecture includes a gap region between memory cells
• Gap region contains a fluid, such as air, with a low dielectric constant
• Low dielectric constant reduces capacitance between plates and eliminates undesirable coupling
• Implementation of the gap region improves memory device speed
• Implementation of the gap region reduces resource consumption associated with memory operations

Potential Applications

• Memory devices in electronic devices such as smartphones, tablets, and computers
• Data storage systems in servers and data centers
• Embedded memory in integrated circuits for various applications

Problems Solved

• Reduces capacitance between plates and eliminates undesirable coupling during memory operations
• Increases memory device speed
• Reduces resource consumption associated with memory operations

Benefits

• Improved performance and efficiency of memory devices
• Faster data access and retrieval
• Reduced power consumption
• Enhanced reliability and longevity of memory devices

Abstract

Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations