17807303. MEMORY SECTION SELECTION FOR A MEMORY BUILT-IN SELF-TEST simplified abstract (Micron Technology, Inc.)
Contents
MEMORY SECTION SELECTION FOR A MEMORY BUILT-IN SELF-TEST
Organization Name
Inventor(s)
Scott E. Schaefer of Boise ID (US)
MEMORY SECTION SELECTION FOR A MEMORY BUILT-IN SELF-TEST - A simplified explanation of the abstract
This abstract first appeared for US patent application 17807303 titled 'MEMORY SECTION SELECTION FOR A MEMORY BUILT-IN SELF-TEST
Simplified Explanation
The abstract describes a method for selecting memory sections for a memory built-in self-test (BIST) in a memory device. Here is a simplified explanation of the abstract:
- The memory device reads a set of bits from a test control mode register to determine the test mode for performing the memory BIST.
- The memory device then reads another set of bits from a section identifier mode register to identify the specific memory sections for which the BIST is to be performed.
- The memory sections selected for the BIST are a subset of the total memory sections in the memory device.
- Finally, the memory device performs the BIST for the selected memory sections based on the test mode.
Potential Applications:
- Memory testing: This technology can be applied in various memory devices, such as RAM, to perform built-in self-tests on specific memory sections, ensuring their proper functioning.
- Quality control: By selectively testing specific memory sections, manufacturers can identify and address any issues or defects in those sections, improving the overall quality of the memory device.
Problems Solved:
- Efficient testing: By allowing the selection of specific memory sections for testing, this technology enables more targeted and efficient memory testing, saving time and resources.
- Fault isolation: By identifying and testing specific memory sections, any faults or failures can be isolated to those sections, making it easier to diagnose and fix issues.
Benefits:
- Customizable testing: The ability to select specific memory sections for testing provides flexibility and customization in the memory BIST process.
- Resource optimization: By testing only the necessary memory sections, resources such as time and power can be optimized, reducing testing overhead.
- Improved reliability: By performing targeted tests on specific memory sections, any potential issues can be identified and resolved, leading to improved overall reliability of the memory device.
Original Abstract Submitted
Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.
