17808043. INTERRUPTING A MEMORY BUILT-IN SELF-TEST simplified abstract (Micron Technology, Inc.)

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INTERRUPTING A MEMORY BUILT-IN SELF-TEST

Organization Name

Micron Technology, Inc.

Inventor(s)

Scott E. Schaefer of Boise ID (US)

INTERRUPTING A MEMORY BUILT-IN SELF-TEST - A simplified explanation of the abstract

This abstract first appeared for US patent application 17808043 titled 'INTERRUPTING A MEMORY BUILT-IN SELF-TEST

Simplified Explanation

The patent application describes a method for interrupting a memory built-in self-test (BIST) in a memory device. Here are the key points:

  • The memory device reads one or more bits stored in a mode register to determine if the memory BIST should be interrupted.
  • The memory device can identify, based on these bits, whether the BIST should be interrupted while it is being performed in a test mode.
  • However, the memory device is not allowed to interrupt the BIST if it is being performed in a repair mode.
  • If the conditions are met, the memory device interrupts the BIST while it is being performed in the test mode.

Potential applications of this technology:

  • Memory testing: This method can be used in memory devices to interrupt the built-in self-test during the testing phase, allowing for more efficient testing processes.
  • Manufacturing: The ability to interrupt the BIST can be useful during the manufacturing process to quickly identify and address any issues with the memory device.

Problems solved by this technology:

  • Efficient testing: By allowing the memory device to interrupt the BIST during the test mode, unnecessary testing time can be saved, improving overall efficiency.
  • Flexibility: The ability to interrupt the BIST based on the mode register bits provides flexibility in controlling the testing process based on specific requirements.

Benefits of this technology:

  • Time-saving: Interrupting the BIST during the test mode can save significant testing time, especially in large-scale memory testing scenarios.
  • Improved control: The mode register bits allow for better control over the testing process, ensuring that the BIST is interrupted only when necessary and not during the repair mode.


Original Abstract Submitted

Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

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