17812233. MEMORY DEVICE ASSEMBLY WITH REDISTRIBUTION LAYER BETWEEN TRANSISTORS AND CAPACITORS simplified abstract (Micron Technology, Inc.)

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MEMORY DEVICE ASSEMBLY WITH REDISTRIBUTION LAYER BETWEEN TRANSISTORS AND CAPACITORS

Organization Name

Micron Technology, Inc.

Inventor(s)

Marcello Mariani of Milano (IT)

Giorgio Servalli of Fara Gera d'Adda (IT)

MEMORY DEVICE ASSEMBLY WITH REDISTRIBUTION LAYER BETWEEN TRANSISTORS AND CAPACITORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17812233 titled 'MEMORY DEVICE ASSEMBLY WITH REDISTRIBUTION LAYER BETWEEN TRANSISTORS AND CAPACITORS

Simplified Explanation

The patent application describes a memory device with an array of memory cells. Each memory cell consists of a transistor and a capacitor. The transistor has a pillar structure with upper and lower source/drain regions and a channel in between. The transistor also has a gate that is part of a gate line and is located near the channel. The memory cell includes a capacitor with a bottom electrode, an insulator, and a top electrode. The memory cell also includes a conductive contact region that connects the transistor and the capacitor.

  • The memory device includes an array of memory cells.
  • Each memory cell consists of a transistor and a capacitor.
  • The transistor has a pillar structure with upper and lower source/drain regions and a channel.
  • The transistor's gate is part of a gate line and is located near the channel.
  • The memory cell includes a capacitor with a bottom electrode, an insulator, and a top electrode.
  • The memory cell also includes a conductive contact region that connects the transistor and the capacitor.
  • The conductive contact region includes the upper source/drain, a first conductive region, and a second conductive region.
  • The first conductive region abuts the upper source/drain and contacts a first insulator line.
  • The second conductive region abuts the upper source/drain and contacts a second insulator line parallel to the first insulator line.

Potential Applications

  • Memory devices for computers, smartphones, and other electronic devices.
  • Storage devices for data centers and cloud computing.
  • Embedded memory in various electronic systems.

Problems Solved

  • Provides a compact and efficient memory cell design.
  • Enables high-density memory arrays.
  • Improves the performance and reliability of memory devices.

Benefits

  • Increased memory capacity in a smaller footprint.
  • Faster data access and retrieval.
  • Enhanced overall performance of electronic devices.
  • Improved energy efficiency.


Original Abstract Submitted

A memory device includes an array of memory cells. A memory cell includes a transistor with a pillar that includes an upper source/drain, a lower source/drain, and a channel between the upper source/drain and the lower source/drain. The transistor includes a gate that is part of a gate line and that is proximate to the channel. The memory cell includes a capacitor having a bottom electrode, an insulator, and a top electrode. The memory cell includes a conductive contact region that couples the transistor and the capacitor and that includes the upper source/drain, a first conductive region having a right surface that abuts the upper source/drain and having a left surface that contacts a first insulator line, and a second conductive region having a left surface that abuts the upper source/drain and having a right surface that contacts a second insulator line that is parallel to the first insulator line.

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