17823371. TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS simplified abstract (Micron Technology, Inc.)
TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS
Organization Name
Inventor(s)
Ferdinando Bedeschi of Biassono (IT)
TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823371 titled 'TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS
Simplified Explanation
Methods, systems, and devices for transistor configurations for vertical memory arrays are described in this patent application. The memory device implements a multi-transistor architecture, specifically a two-transistor architecture, to connect pillars with bit lines. Here is a simplified explanation of the abstract:
- The memory device includes a conductive pillar that extends through different levels of the memory array.
- The pillar is connected to a first bit line through a first transistor and to a second bit line through a second transistor.
- To access a memory cell connected to the pillar, the memory device biases a word line connected to the memory cell to a first access voltage.
- One of the bit lines is biased to a second access voltage, and one of the transistors is activated to connect the pillar with that bit line.
- The other transistor is deactivated to isolate the pillar from the other bit line.
Potential Applications
This technology has potential applications in various fields, including:
- Memory devices and systems
- Semiconductor manufacturing
- Data storage and retrieval systems
Problems Solved
The patent addresses the following problems:
- Efficiently connecting conductive pillars with bit lines in a vertical memory array
- Enabling access to specific memory cells in the array
- Isolating the conductive pillars from unwanted bit lines
Benefits
The benefits of this technology include:
- Improved performance and efficiency of memory devices
- Enhanced data storage and retrieval capabilities
- Simplified transistor configurations for vertical memory arrays
Original Abstract Submitted
Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.
