17864192. PLANE BALANCING IN A MEMORY SYSTEM simplified abstract (Micron Technology, Inc.)
Contents
PLANE BALANCING IN A MEMORY SYSTEM
Organization Name
Inventor(s)
John J. Kane of Westminster CO (US)
Byron D. Harris of Mead CO (US)
Vivek Shivhare of Milpitas CA (US)
PLANE BALANCING IN A MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 17864192 titled 'PLANE BALANCING IN A MEMORY SYSTEM
Simplified Explanation
Methods, systems, and devices for plane balancing in a memory system are described in this patent application. The memory system selects a memory die for writing a set of data, which consists of a plurality of planes, each containing multiple blocks of memory cells. The memory system determines the availability status of blocks in two different planes and writes the data to the planes based on the quantity of available blocks.
- The memory system selects a memory die for writing data.
- The memory die consists of multiple planes, each containing blocks of memory cells.
- The memory system determines the availability status of blocks in two different planes.
- The system writes the data to the planes, excluding the plane with the highest quantity of blocks with the availability status.
- The decision of which planes to write the data to is based on the quantity of available blocks in each plane.
Potential Applications
- Memory systems in electronic devices such as smartphones, tablets, and computers.
- Data storage systems in servers and data centers.
Problems Solved
- Balancing the usage of memory planes in a memory system.
- Preventing overuse of specific planes, which can lead to performance degradation and reduced lifespan of the memory system.
Benefits
- Improved performance and reliability of memory systems.
- Extended lifespan of memory systems by evenly distributing the usage across planes.
- Efficient utilization of memory resources.
Original Abstract Submitted
Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.
