17858731. ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION simplified abstract (Micron Technology, Inc.)

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ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION

Organization Name

Micron Technology, Inc.

Inventor(s)

Charles See Yeung Kwong of Redwood City CA (US)

Seungjune Jeon of Santa Clara CA (US)

Wei Wang of Dublin CA (US)

Zhenming Zhou of San Jose CA (US)

ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17858731 titled 'ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION

Simplified Explanation

The abstract describes a method for managing the reliability of memory devices by identifying blocks within the memory and associating them with a capability metric that reflects the projected reliability of the underlying components. If the capability metric meets a certain condition, a cycle threshold is determined for the block. When the program/erase cycle counter reaches the cycle threshold, the block is excluded from the set of blocks and a program operation is performed on the updated set.

  • Identifying blocks of a memory device and associating them with a capability metric reflecting the projected reliability of the underlying components.
  • Determining a cycle threshold for a block based on the capability metric.
  • Updating the set of blocks by excluding a block when the program/erase cycle counter matches the cycle threshold.
  • Performing a program operation on the updated set of blocks.

Potential Applications

  • Memory management in electronic devices.
  • Improving the reliability and lifespan of memory devices.

Problems Solved

  • Ensuring the reliability of memory devices by monitoring and managing the program/erase cycles.
  • Optimizing the use of memory blocks based on their projected reliability.

Benefits

  • Increased reliability and lifespan of memory devices.
  • Efficient utilization of memory blocks.
  • Improved performance and longevity of electronic devices.


Original Abstract Submitted

A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.