17829576. System And Method To Control Memory Error Detection With Automatic Disabling simplified abstract (Micron Technology, Inc.)
System And Method To Control Memory Error Detection With Automatic Disabling
Organization Name
Inventor(s)
Parthasarathy Gajapathy of McKinney TX (US)
David R. Brown of Allen TX (US)
System And Method To Control Memory Error Detection With Automatic Disabling - A simplified explanation of the abstract
This abstract first appeared for US patent application 17829576 titled 'System And Method To Control Memory Error Detection With Automatic Disabling
Simplified Explanation
The abstract describes a memory device that includes a command interface, an input output interface, and error detection circuitry. The error detection circuitry generates signals based on different periods of time and clock signals to make determinations about data signals.
- The memory device has a command interface to receive write commands.
- It also has an input output interface to receive data signals along with the write command.
- The error detection circuitry is connected to the input output interface.
- The error detection circuitry generates a first signal to determine a first portion of the data signals using a first data strobe signal as a clock.
- It also generates a second signal to determine a second portion of the data signals using a second data strobe signal as a clock.
- The error detection circuitry generates a control signal based on the first signal, the second signal, and the slower of the two data strobe signals.
Potential Applications
- This memory device can be used in various electronic devices that require reliable and accurate data storage and retrieval.
- It can be implemented in computer systems, servers, mobile devices, and other electronic devices that use memory for data storage.
Problems Solved
- The error detection circuitry helps in identifying and correcting errors in the data signals received by the memory device.
- By using different clock signals and periods of time, the memory device can accurately determine and handle different portions of the data signals.
Benefits
- The memory device provides improved error detection and correction capabilities, ensuring data integrity.
- It allows for efficient and reliable data storage and retrieval.
- The use of different clock signals and periods of time enhances the accuracy and efficiency of data processing in the memory device.
Original Abstract Submitted
A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.
