17830108. Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract (Micron Technology, Inc.)
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
Organization Name
Inventor(s)
John D. Hopkins of Meridian ID (US)
Nancy M. Lomeli of Boise ID (US)
Jordan D. Greenlee of Boise ID (US)
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A simplified explanation of the abstract
This abstract first appeared for US patent application 17830108 titled 'Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
Simplified Explanation
The abstract describes a method for forming a memory array using memory cells. Here are the key points:
- The method involves creating a conductor tier on a substrate.
- Memory-block regions are formed above the conductor tier, consisting of alternating first and second tiers.
- Channel-material strings pass through these tiers.
- Conducting material is formed in the lower first tier, connecting the channel material and the conductor material.
- The conducting material has an upper portion, a lower portion, and a void-space in between.
- Silicon is selectively deposited into the void-space, onto and from the exposed silicon-containing surface.
Potential applications of this technology:
- Memory arrays in electronic devices
- Data storage systems
- Computer memory modules
Problems solved by this technology:
- Efficient formation of memory arrays
- Improved connectivity between memory cells and conductor material
Benefits of this technology:
- Higher memory density
- Faster data transfer
- Enhanced reliability and durability of memory arrays
Original Abstract Submitted
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.
