17887244. VOLTAGE WINDOW ADJUSTMENT simplified abstract (Micron Technology, Inc.)
Contents
VOLTAGE WINDOW ADJUSTMENT
Organization Name
Inventor(s)
Zhenming Zhou of San Jose CA (US)
Nagendra Prasad Ganesh Rao of Folsom CA (US)
Joshua C. Garrison of Folsom CA (US)
VOLTAGE WINDOW ADJUSTMENT - A simplified explanation of the abstract
This abstract first appeared for US patent application 17887244 titled 'VOLTAGE WINDOW ADJUSTMENT
Simplified Explanation
The patent application describes a system that includes a memory component and a processing device. The memory component consists of a group of memory cells, while the processing device is connected to the memory component.
- The processing device is programmed to use a specific voltage window for a set of memory cells during a certain time period.
- If the processing device detects that the error rate of a subset of the memory cells exceeds a predefined threshold, it will take action.
- In response to the high error rate, the processing device will switch to a different voltage window for the entire set of memory cells during a different time period.
Potential applications of this technology:
- This technology can be used in computer systems, particularly in memory components, to improve error detection and correction.
- It can be applied in various industries that rely on reliable and accurate data storage, such as telecommunications, data centers, and cloud computing.
Problems solved by this technology:
- Memory cells can sometimes experience errors, which can lead to data corruption or loss.
- By monitoring the error rate and adjusting the voltage window accordingly, this technology helps to identify and mitigate errors in memory cells.
Benefits of this technology:
- Improved reliability and accuracy of data storage.
- Enhanced error detection and correction capabilities.
- Increased overall system performance and efficiency.
Original Abstract Submitted
An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.
