17888472. MULTIPLE, ALTERNATING EPITAXIAL SILICON simplified abstract (Micron Technology, Inc.)

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MULTIPLE, ALTERNATING EPITAXIAL SILICON

Organization Name

Micron Technology, Inc.

Inventor(s)

John F. Kaeding of Boise ID (US)

Matthew S. S. Thorum of Boise ID (US)

MULTIPLE, ALTERNATING EPITAXIAL SILICON - A simplified explanation of the abstract

This abstract first appeared for US patent application 17888472 titled 'MULTIPLE, ALTERNATING EPITAXIAL SILICON

Simplified Explanation

The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes. The access devices have two source/drain regions separated by a single crystalline silicon channel region. The access lines connect to gates surrounding the channel region, forming gate all around (GAA) structures. Vertical digit lines are connected to the source/drain regions.

  • The patent application proposes a new design for vertically stacked memory cells.
  • The access devices have horizontally oriented structures with two source/drain regions and a single crystalline silicon channel region.
  • The access lines are connected to gates that surround the channel region, forming gate all around (GAA) structures.
  • Vertical digit lines are connected to the source/drain regions of the access devices.

Potential applications of this technology:

  • Memory devices in electronic devices such as smartphones, tablets, and computers.
  • Data storage in cloud computing and data centers.
  • High-performance computing systems.

Problems solved by this technology:

  • The design allows for vertically stacked memory cells, increasing the storage capacity in a smaller footprint.
  • The horizontally oriented access devices provide efficient access to the storage nodes.
  • The gate all around (GAA) structures improve the performance and reliability of the memory cells.

Benefits of this technology:

  • Increased storage capacity in a smaller footprint.
  • Improved performance and reliability of the memory cells.
  • Efficient access to the storage nodes.


Original Abstract Submitted

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source/drain regions.

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