17887362. INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE simplified abstract (Micron Technology, Inc.)
INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE
Organization Name
Inventor(s)
Vijayakrishna J. Vankayala of Allen TX (US)
INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17887362 titled 'INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE
Simplified Explanation
The patent application describes techniques for reducing inter-die signal loads within a multi-die package. The package includes a first memory die and at least one second memory die connected via an inter-die connection. The technique involves adding an additional wirebond pad to each die in the package. When making the inter-die connections, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. This allows the first memory die to transmit inter-die signals to the second memory die with a lower signal load within the multi-die package.
- Additional wirebond pads are added to each die in a multi-die package.
- The wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die.
- This reduces inter-die signal loads within the multi-die package.
Potential Applications
- Multi-die packages in electronic devices such as smartphones, tablets, and computers.
- Memory modules in data centers and servers.
Problems Solved
- Reduces inter-die signal loads, improving signal integrity and reducing noise within the multi-die package.
- Enables efficient communication between memory dies in a multi-die package.
Benefits
- Improved performance and reliability of multi-die packages.
- Enhanced signal integrity and reduced noise.
- Cost-effective solution for reducing inter-die signal loads.
Original Abstract Submitted
Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.
