17829737. Pre-Sense Gut Node Amplification in Sense Amplifier simplified abstract (Micron Technology, Inc.)
Pre-Sense Gut Node Amplification in Sense Amplifier
Organization Name
Inventor(s)
Christopher K. Morzano of Boise ID (US)
Christopher J. Kawamura of Boise ID (US)
Charles L. Ingalls of Meridian ID (US)
Pre-Sense Gut Node Amplification in Sense Amplifier - A simplified explanation of the abstract
This abstract first appeared for US patent application 17829737 titled 'Pre-Sense Gut Node Amplification in Sense Amplifier
Simplified Explanation
The patent application describes a memory device that includes multiple memory cells and digit lines for data storage and transfer. The device also includes multiple sense amplifiers that are selectively connected to the digit lines.
- The sense amplifiers perform threshold compensation for NMOS transistors by storing voltages proportional to their respective threshold voltages.
- The sense amplifiers amplify the differential voltage between the two nodes by charging one node and discharging the other node based on the charges of the digit lines.
Potential Applications
- Memory devices in computer systems
- Solid-state drives (SSDs)
- Mobile devices such as smartphones and tablets
Problems Solved
- Threshold compensation helps in maintaining accurate data storage and retrieval in memory cells.
- Amplification of differential voltage improves the signal-to-noise ratio and enhances data transfer efficiency.
Benefits
- Improved reliability and accuracy of data storage and retrieval in memory devices.
- Enhanced performance and efficiency of memory devices.
- Higher signal-to-noise ratio for better data transfer quality.
Original Abstract Submitted
A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.
