17859468. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES

Organization Name

Micron Technology, Inc.

Inventor(s)

Vamsi Pavan Rayaprolu of Santa Clara CA (US)

Mustafa N. Kaynak of San Diego CA (US)

Sivagnanam Parthasarathy of Carlsbad CA (US)

Patrick Khayat of San Diego CA (US)

Sampath Ratnam of San Jose CA (US)

Kishore Kumar Muchherla of Fremont CA (US)

Jiangang Wu of Milpitas CA (US)

James Fitzpatrick of Laguna Niguel CA (US)

MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17859468 titled 'MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES

Simplified Explanation

The patent application describes a system and method for maintaining data integrity in a memory device. Here is a simplified explanation of the abstract:

• The system includes a memory device and a processing device.
• The processing device performs operations on a set of memory cells that are configured to store a certain number of bits per cell.
• A data integrity check is performed on the memory cells to determine the data integrity metric value.
• The data integrity metric value is compared to a threshold criterion to determine if it meets the required level of integrity.
• If the data integrity metric value fails to meet the threshold criterion, the data from the source set of memory cells is copied to a different set of memory cells that can store a different number of bits per cell.

Potential applications of this technology:

• Data storage devices such as solid-state drives (SSDs) and flash memory devices.
• Cloud storage systems.
• Database systems.

Problems solved by this technology:

• Ensures data integrity in memory devices by performing data integrity checks.
• Provides a mechanism to copy data to a different set of memory cells if the integrity check fails.

Benefits of this technology:

• Improves the reliability and integrity of stored data.
• Reduces the risk of data corruption and loss.
• Allows for efficient use of memory cells by utilizing different configurations based on data integrity requirements.

Original Abstract Submitted

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.