17830169. TEST MODE STATE MACHINE FOR A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)

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TEST MODE STATE MACHINE FOR A MEMORY DEVICE

Organization Name

Micron Technology, Inc.

Inventor(s)

Rucha Deepak Geedh of Folsom CA (US)

Manjinder Singh Bains of Yuba City CA (US)

Roopal Amit Patel of Folsom CA (US)

TEST MODE STATE MACHINE FOR A MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17830169 titled 'TEST MODE STATE MACHINE FOR A MEMORY DEVICE

Simplified Explanation

The patent application describes a memory device that is capable of self-testing using test mode state machines. The memory device includes a memory array with memory cells and periphery logic that receives a command from a host device to initiate self-testing. The periphery logic generates trigger signals in response to the command. The memory device also includes control circuitry with state machines that receive the trigger signals and execute a command sequence, which includes read, write, or delay operations. Each partition of the memory array can have its own integrated state machine.

  • Memory device with self-testing capabilities using test mode state machines
  • Memory array with memory cells and periphery logic
  • Periphery logic receives a command from a host device to initiate self-testing
  • Periphery logic generates trigger signals in response to the command
  • Control circuitry with state machines receives the trigger signals and executes a command sequence
  • Command sequence includes read, write, or delay operations
  • Each partition of the memory array can have its own integrated state machine

Potential Applications

  • Memory devices used in various electronic devices such as computers, smartphones, and tablets
  • Testing and quality control of memory devices during manufacturing process

Problems Solved

  • Provides a self-testing mechanism for memory devices, reducing the need for external testing equipment
  • Allows for efficient and automated testing of memory devices during manufacturing process

Benefits

  • Simplifies the testing process for memory devices
  • Reduces the cost and time associated with external testing equipment
  • Improves the overall quality and reliability of memory devices


Original Abstract Submitted

Systems, methods, and apparatus for a memory device having test mode state machines configured to perform self-testing. In one approach, a memory array has memory cells. Periphery logic of the memory device receives a command from a host device to initiate self-testing. The periphery logic generates trigger signal(s) in response to receiving the command. Control circuitry (e.g., a controller) has state machine(s) that receives the trigger signal(s) and initiates execution of a command sequence. The command sequence includes various orders of operations such as read, write, or delay. A state machine can be integrated into each of multiple partitions of the memory array.

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