17834414. Error Detection in Communications over Serial Peripheral Interfaces simplified abstract (Micron Technology, Inc.)

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Error Detection in Communications over Serial Peripheral Interfaces

Organization Name

Micron Technology, Inc.

Inventor(s)

Minjian Wu of Shanghai (CN)

Error Detection in Communications over Serial Peripheral Interfaces - A simplified explanation of the abstract

This abstract first appeared for US patent application 17834414 titled 'Error Detection in Communications over Serial Peripheral Interfaces

Simplified Explanation

The abstract describes a memory device and a host system that use serial peripheral interfaces to transmit data. The data is followed by a cyclic redundancy check (CRC) value, which is used to verify the accuracy of the data transmission. If the received CRC value does not match the computed CRC value, an interrupt signal is sent to request re-transmission of the data.

  • The memory device and host system use serial peripheral interfaces to transmit data and CRC values.
  • The CRC value is used to check the accuracy of the data transmission.
  • If the received CRC value does not match the computed CRC value, an interrupt signal is sent to request re-transmission.
  • The host system can terminate a read command and re-transmit it if a transmission error is detected.

Potential Applications

  • This technology can be used in various memory devices and host systems that utilize serial peripheral interfaces.
  • It can be applied in systems where data integrity is crucial, such as in communication devices, storage devices, and embedded systems.

Problems Solved

  • Ensures the accuracy of data transmission by using CRC values to detect errors.
  • Provides a mechanism for requesting re-transmission of data when errors are detected.
  • Allows the host system to terminate and re-transmit commands in case of transmission errors.

Benefits

  • Improved data integrity by verifying the accuracy of data transmission.
  • Efficient error detection and re-transmission mechanism.
  • Enhances the reliability and performance of memory devices and host systems.


Original Abstract Submitted

A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.

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