17830145. MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS simplified abstract (Micron Technology, Inc.)
MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
Organization Name
Inventor(s)
Sheyang Ning of San Jose CA (US)
MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17830145 titled 'MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
Simplified Explanation
Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described in this patent application. The memory device includes a memory array with multiple levels of memory cells, each separated by a dielectric layer. Each memory cell at a first level includes a channel portion and a capacitor to store its logic state. The capacitor has a first portion located between the channel portion and a voltage source, and a second portion in a cavity in a dielectric layer between the first and second levels of the memory array. The second portion of the capacitor is located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.
- Memory device with multiple levels of memory cells
- Capacitor structure to store logic state of memory cells
- First portion of capacitor located between channel portion and voltage source
- Second portion of capacitor in a cavity in a dielectric layer between levels
- Second portion of capacitor located between channel portion and word line of second memory cell
Potential Applications
- Three-dimensional memory arrays
- High-density memory devices
- Data storage in electronic devices
Problems Solved
- Increasing memory density in limited space
- Efficient storage of logic states in memory cells
- Reducing interference between memory cells
Benefits
- Higher memory capacity in smaller footprint
- Improved performance and reliability of memory devices
- Enhanced data storage capabilities in electronic devices
Original Abstract Submitted
Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.
