18454703. METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS simplified abstract (Micron Technology, Inc.)

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS

Organization Name

Micron Technology, Inc.

Inventor(s)

Sameer S. Vadhavkar of Boise ID (US)

Xiao Li of Boise ID (US)

Steven K. Groothuis of Boise ID (US)

Jian Li of Boise ID (US)

Jaspreet S. Gandhi of Boise ID (US)

James M. Derderian of Boise ID (US)

David R. Hembree of Boise ID (US)

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18454703 titled 'METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS

Simplified Explanation

The abstract describes a method for packaging a semiconductor die assembly. The method involves coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The thermal transfer structure limits the lateral flow of the underfill material.

• The method involves packaging a semiconductor die assembly with a first die and multiple second dies stacked on top of it.
• The first die has a peripheral region extending outward from the stack of second dies.
• A thermal transfer structure is attached to the peripheral region of the first die.
• An underfill material is then flowed between the second dies.
• The thermal transfer structure prevents the underfill material from flowing laterally.

Potential applications of this technology:

• Semiconductor packaging industry
• Electronics manufacturing

Problems solved by this technology:

• Prevents lateral flow of underfill material, which can cause damage or malfunction in the semiconductor die assembly.

Benefits of this technology:

• Improved reliability and performance of semiconductor die assemblies
• Enhanced thermal management
• Reduced risk of damage or malfunction due to underfill material flow.

Original Abstract Submitted

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.