18204773. FORMATION FOR MEMORY CELLS simplified abstract (Micron Technology, Inc.)
Contents
FORMATION FOR MEMORY CELLS
Organization Name
Inventor(s)
Giorgio Servalli of Fara Gera d'Adda (IT)
Durai Vishak Nirmal Ramaswamy of Boise ID (US)
Marcello Mariani of Milano (IT)
FORMATION FOR MEMORY CELLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18204773 titled 'FORMATION FOR MEMORY CELLS
Simplified Explanation
The patent application describes methods, systems, and devices for forming memory cells. Specifically, it focuses on a semiconductor device (such as a memory die) that includes asymmetrical rows of conductive pillars and one or more dielectric materials. The memory die has a set of conductive pillars arranged in rows with different spacing distances. Additionally, the memory die includes one or more dielectric materials that conformally line exposed surfaces during a self-aligning process.
- The patent application describes a semiconductor device with asymmetrical rows of conductive pillars and dielectric materials.
- The conductive pillars are arranged in rows with different spacing distances.
- The dielectric materials conformally line exposed surfaces during a self-aligning process.
- This reduces the need for subsequent masking operations in the formation of the memory die.
Potential Applications
- Memory devices
- Semiconductor manufacturing
Problems Solved
- Decreases the number of masking operations required in the formation of memory dies.
- Provides a self-aligning process for depositing dielectric materials.
Benefits
- Simplifies the formation process of memory cells.
- Reduces manufacturing time and cost.
- Improves the efficiency of memory device production.
Original Abstract Submitted
Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.
