17864046. TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS simplified abstract (Micron Technology, Inc.)

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TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS

Organization Name

Micron Technology, Inc.

Inventor(s)

Ferdinando Bedeschi of Biassono (MB) (IT)

Efrem Bolandrina of Fiorano al Serio (BG) (IT)

Innocenzo Tortorelli of Cernusco sul Naviglio (MI) (IT)

TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17864046 titled 'TIMING FOR OPERATIONS IN MEMORY DEVICE STORING BITS IN MEMORY CELL PAIRS

Simplified Explanation

The patent application describes a memory device that uses storage class memory, such as flash memory.

  • The memory device has a memory array consisting of memory cells arranged as differential memory cell pairs.
  • Each memory cell pair stores a single logical bit.
  • The memory device is controlled by a controller that receives commands from a host to perform read operations.
  • The memory cell pair is selected using bitlines and a common wordline.
  • A partition of the memory array is accessed to read the data stored by the memory cell pair.
  • The read data is then stored in a latch for sending to the host.
  • A counter is incremented in response to accessing the partition.
  • The controller uses statistical analysis to determine whether to perform a refresh operation for the partition.
  • The determination is based on comparing the current value of the counter to a value previously generated by a random number generator.

Potential Applications

  • This technology can be applied in various memory devices, such as solid-state drives (SSDs) and other storage devices.
  • It can be used in computer systems, servers, and other electronic devices that require high-performance memory.

Problems Solved

  • The technology solves the problem of efficiently reading data from memory cells in a memory device.
  • It addresses the issue of determining when to perform a refresh operation for memory partitions to maintain data integrity.

Benefits

  • The memory device allows for efficient read operations by accessing specific memory cell pairs and storing the read data in a latch.
  • The statistical analysis performed by the controller helps optimize the refresh operation, reducing unnecessary refresh cycles.
  • By using a random number generator, the refresh operation can be performed in a more balanced and controlled manner, improving overall memory performance and reliability.


Original Abstract Submitted

Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.

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