17860021. PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE simplified abstract (Micron Technology, Inc.)

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PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE

Organization Name

Micron Technology, Inc.

Inventor(s)

Shruti Jain of Boise ID (US)

Anton P. Eppich of Boise ID (US)

PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17860021 titled 'PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE

Simplified Explanation

The patent application describes a 3D memory device that consists of a stack of supporting lattice layers and dielectric layers on a substrate. The device includes memory pillars that vertically penetrate the stack and are made up of vertically connected replacement gate (RG) memory cells. Additionally, there are supporting buttress (SBT) pillars located at the outside ends of the memory pillars that vertically penetrate the stack. The memory pillars and SBT pillars are laterally connected by the supporting lattice layers.

  • The memory device is three-dimensional and includes a stack of supporting lattice layers and dielectric layers.
  • Memory pillars are present in the device and vertically penetrate the stack.
  • The memory pillars consist of vertically connected replacement gate (RG) memory cells.
  • The memory pillars have a square shape in a horizontal plane parallel to the supporting lattice layers.
  • Supporting buttress (SBT) pillars are located at the outside ends of the memory pillars and also vertically penetrate the stack.
  • The memory pillars and SBT pillars are laterally connected by the supporting lattice layers.

Potential Applications

  • This 3D memory device can be used in various electronic devices such as computers, smartphones, and tablets.
  • It can be utilized in data storage systems, allowing for increased memory capacity in a smaller form factor.
  • The device can be integrated into artificial intelligence systems, enabling faster and more efficient data processing.

Problems Solved

  • The 3D memory device solves the problem of limited memory capacity in electronic devices by utilizing a vertical stacking approach.
  • It addresses the need for smaller and more compact memory solutions without compromising performance.
  • The device solves the challenge of increasing data processing requirements by providing a higher density of memory cells.

Benefits

  • The 3D memory device offers increased memory capacity compared to traditional two-dimensional memory structures.
  • It allows for a smaller form factor, enabling the development of more compact and portable electronic devices.
  • The device provides faster data processing and improved performance due to the vertically connected memory cells.


Original Abstract Submitted

A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first square peripheral shape in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

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