Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on November 9th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on November 9th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. has recently filed several patents related to memory devices and semiconductor structures. These patents cover various aspects such as memory stack formation, semiconductor structure design, memory cell fabrication, and ferroelectric memory devices.

Summary: - The patents describe memory stacks consisting of bottom and top electrode layers, a phase change layer, and a rough portion on the top electrode layer. - A semiconductor structure is disclosed, featuring a storage element layer and a selector with multiple insulating and conductive layers. - A memory device is described, comprising a substrate, a spin-orbit torque layer, and a magnetic tunneling junction (MTJ) with a synthetic free layer, barrier layer, and reference layer. - A method for forming a memory cell involves depositing a memory film, a hard mask film, and performing trimming and etching processes. - A bipolar selector with independently tunable threshold voltages is introduced, along with a memory cell and memory array comprising the selector. - An integrated chip is disclosed, including a magnetic tunnel junction, two unipolar selectors, and their electrical connections. - A ferroelectric random-access memory (FeRAM) cell is presented, featuring a bottom electrode, switching layer, and top electrode with an interface structure to prevent diffusion. - A semiconductor device is described, consisting of a semiconductor substrate, memory gate, and data storage element made of a ferroelectric material. - A semiconductor structure is disclosed, comprising a substrate, stacked structure with insulating layers and gate members, and a core structure with memory layer, channel member, contact member, and liner member. - A method of forming a ferroelectric memory device involves atomic layer deposition (ALD) to create a ferroelectric layer with an orthorhombic phase (O-phase).

Notable Applications:

• Memory stack formation and semiconductor structure design for improved memory devices.
• Ferroelectric memory cell fabrication with enhanced endurance and prevention of leakage current.
• Tunable threshold voltages in bipolar selectors for improved performance in memory cells and arrays.
• Integration of magnetic tunnel junctions and unipolar selectors in an integrated chip for magnetic memory storage.
• Atomic layer deposition for the formation of ferroelectric memory devices with enhanced ferroelectric polarization.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 9th, 2023

OPTICAL DETECTION FOR BIO-ENTITIES (18353603)

Main Inventor

Allen Timothy Chang

Brief explanation

The patent application describes an integrated semiconductor device for manipulating and processing bio-entity samples. 

• The device includes a lower substrate, which serves as the base for the device.
• It also includes at least one optical signal conduit, which is used to transmit optical signals.
• The device has at least one cap bonding pad, which is used for bonding the cap to the lower substrate.
• A cap is included in the device, which forms a capped area and is placed on the cap bonding pad.
• The device has a fluidic channel, which is formed on both the lower substrate and the cap.
• The device includes a photosensor array, which is connected to sensor control circuitry. This allows for the detection and processing of optical signals.
• The device also includes logic circuitry, which is connected to both the fluidic control circuitry and the sensor control circuitry. This allows for the control and processing of the fluidic channel and the photosensor array.

Abstract

An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.

THERMAL SENSOR USING INVERSION DIFFUSIVITY RESISTANCE (17735887)

Main Inventor

Jaw-Juinn Horng

Brief explanation

The patent application describes a device that consists of multiple metal-oxide semiconductor field-effect transistors (MOSFETs) connected in series. Each MOSFET has a gate structure, a drain/source region on one side, and another drain/source region on the other side. The gate structure of each MOSFET is designed to receive a bias voltage, which turns on the MOSFETs and allows them to provide a temperature-dependent resistance. This resistance is then used to measure temperatures.

• The device includes multiple MOSFETs connected in series.
• Each MOSFET has a gate structure, drain/source regions, and is biased with a voltage.
• The MOSFETs provide a temperature-dependent resistance.
• The resistance is used for temperature measurement.

Abstract

A device including a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series. Each of the first plurality of metal-oxide semiconductor field-effect transistors includes a first gate structure, a first drain/source region on one side of the first gate structure, and a second drain/source region on another side of the first gate structure. The first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.

CONCENTRATION DETERMINATION METHOD (17736105)

Main Inventor

Tung-Tsun Chen

Brief explanation

The patent application describes a method for determining the concentration of a target material in a sample fluid using a bio-sensing integrated circuit.

• Dilution: The sample fluid is diluted with a specific dilution factor to create multiple diluted samples.
• Bio-sensing integrated circuit: A specialized circuit is used for bio-sensing, which can detect the presence of the target material.
• Application: The diluted samples are applied to the bio-sensing circuit for analysis.
• Measurement: The bio-sensing process provides measurement values for each diluted sample.
• Comparison: The measurement values are compared with a threshold value to identify the largest dilution factor that still produces a measurement value above the threshold.
• Concentration calculation: The concentration of the target material is calculated based on the identified dilution factor and a limit of detection.

Abstract

A concentration determination method includes the following steps. A sample fluid having a target material therein is diluted with a 1dilution factor to an Ndilution factor to form a 1sample to an Nsample. A bio-sensing integrated circuit having a 1assay to an Nassay is provided. The 1sample to the Nsample are respectively applied to the 1assay to the Nassay. A bio-sensing process is performed on the 1sample to the Nsample to obtain a 1measurement value to an Nmeasurement value. The 1measurement value to the Nmeasurement value are compared with a threshold value to determine a threshold dilution factor, which corresponds to a largest dilution factor that has a measurement value higher than the threshold value. A concentration of the target material is calculated based on the threshold dilution factor and a limit of detection.

PROBE CARD SUBSTRATE, SUBSTRATE STRUCTURE AND METHOD OF FABRICATING THE SAME (17738023)

Main Inventor

Wei-Yu Chen

Brief explanation

The patent application describes a substrate structure that includes several components such as a core substrate, a redistribution layer, test pads, a protective coating, a conductive pad, and a passive device.

• The substrate structure consists of a core substrate, which serves as the main foundation.
• A redistribution layer is placed on top of the core substrate and is electrically connected to it.
• Test pads are located on the redistribution layer, providing a means for testing and measuring electrical signals.
• A protective coating is applied to the test pads, ensuring their durability and preventing damage.
• A conductive pad is positioned on the redistribution layer alongside the test pads, serving as a connection point for electrical signals.
• A passive device is placed on the conductive pad and is electrically connected to it, allowing for the manipulation or control of electrical signals.

Abstract

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

APPARATUS, PROCESSING CIRCUITRY AND METHOD FOR MEASURING DISTANCE FROM DIRECT TIME OF FLIGHT SENSOR ARRAY TO AN OBJECT (17737030)

Main Inventor

Chin Yin

Brief explanation

This patent application describes an apparatus, processing circuitry, and method for measuring the distance to an object using a direct time of flight (DTOF) sensor array and photon detection signals.

• The apparatus includes a light source and a DTOF sensor array that receives a reflected signal from the object.
• The processing circuitry, which is connected to the DTOF sensor array, includes a first time to digital converter (TDC) and a second TDC placed on opposite sides of the DTOF sensor array.
• The processing circuitry receives a first photon detection signal transmitted by a first pixel through the first TDC and a second photon detection signal transmitted by the same first pixel through the second TDC.
• The processing circuitry calculates the distance from the first pixel to the object by analyzing the arrival times of the photon detection signals detected by the first and second TDCs.

This innovation allows for accurate distance measurement by utilizing photon detection signals and TDCs on opposite sides of the sensor array.

Abstract

An apparatus, a processing circuitry and a method for measuring a distance to an object are provided. The apparatus comprising a light source, a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, a processing circuitry coupled to the DTOF sensor array and comprising a first time to digital converter (TDC) and a second TDC, respectively disposed on opposite sides of the DTOF sensor array, the processing circuitry configured to receive, by the first TDC, a first photon detection signal transmitted by a first pixel, receive, by the second TDC, a second photon detection signal transmitted by the first pixel, and calculate a first distance from the first pixel to the object according to a first arrival time of the first photon detection signal detected by the first TDC and a second arrival time of the second signal detected by the second TDC.

PACKAGE, OPTICAL DEVICE, AND MANUFACTURING METHOD OF PACKAGE (18354662)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a package that includes a photonic integrated circuit die and an electric integrated circuit die.

• The photonic integrated circuit die consists of a substrate and a waveguide.
• The substrate has a notch that is filled with air.
• The waveguide is placed over the substrate, with a portion overlapping the substrate and another portion overlapping the notch.
• The electric integrated circuit die is positioned on top of the photonic integrated circuit die.

Abstract

A package includes a photonic integrated circuit die and an electric integrated circuit die. The photonic integrated circuit die includes a substrate and a waveguide. The substrate has a notch and the notch is occupied by air. The waveguide is disposed over the substrate. In a top view, a first portion of the waveguide is overlapped with the substrate and a second portion of the waveguide is overlapped with the notch. The electric integrated circuit die is disposed over the photonic integrated circuit die.

SUBSTRATE STAGE AND SUBSTRATE PROCESSING SYSTEM USING THE SAME (18351571)

Main Inventor

Yu-Huan CHEN

Brief explanation

The patent application describes a semiconductor substrate stage used for carrying a substrate.

• The stage includes a base layer, a magnetic shielding layer, a carrier layer, a receiver, a storage layer, and a magnetic shielding element.
• The magnetic shielding layer is placed on top of the base layer.
• The carrier layer is placed on top of the magnetic shielding layer.
• The receiver is placed on top of the carrier layer.
• The storage layer is located between the base layer and the magnetic shielding layer.
• The magnetic shielding element surrounds the receiver on the carrier layer.
• The purpose of the magnetic shielding layer and element is to protect the receiver from external magnetic interference.
• The stage is designed to provide a stable and secure platform for carrying a semiconductor substrate.

Abstract

A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver.

METHOD, SYSTEM AND NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR REDUCING WORK-IN-PROCESS (18337021)

Main Inventor

Po-Yi Wang

Brief explanation

The patent application describes a method for improving the cycle time of a product manufacturing process. 

• Collecting process profile data from multiple tool groups running the process
• Calculating key-performance-indicators (KPIs) for each tool group, including the standard deviation of output from a bottleneck tool group
• Using a neural network model to analyze the KPI values and work-in-progress (WIP) of each tool group
• Determining the impact of each KPI on the WIP for each tool group
• Selecting a set of major KPIs for each tool group based on their impact
• Controlling the tool groups based on the major KPIs to reduce the total WIP.

Abstract

A method for improving a cycle time of a process of a product is provided. The method includes: collecting process profile data from a plurality of tool groups running the process, and calculating values of a plurality of key-performance-indicators (KPIs) of each tool group including calculating a standard deviation of an output of a stage of a bottleneck tool group of the tool groups; feeding the values of the KPIs and a work-in-progress (WIP) of each tool group into a neural network model in order to output an impact on the WIP for each KPI of each tool group by the neural network model; selecting a set of major KPIs of each tool group from the KPIs according to the impact of each tool group; and controlling the tool groups according to the impact of the set of major KPIs of each tool group in order to reduce a total WIP.

INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM (18347928)

Main Inventor

Tien-Chien HUANG

Brief explanation

The patent application describes a system for generating layout diagrams of integrated circuit (IC) devices. 

• The system includes a processor and computer code stored in a storage medium.
• The processor uses the computer code to perform various tasks.
• The processor first extracts a netlist, which is a representation of the IC layout diagram focusing on capacitance.
• It then obtains a simulation result based on the extracted netlist.
• The netlist is revised by removing a dummy gate region.
• Another simulation result is obtained based on the revised netlist.
• The first simulation result is compared to the second simulation result.
• The purpose of the comparison is to determine the impact of leakage on the design of the IC device.

Abstract

An integrated circuit (IC) layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to generate a layout diagram of an IC device by performing a capacitance-only netlist extraction on an IC layout diagram, obtaining a first simulation result based on the extracted netlist, revising the extracted netlist by removing the dummy gate region, obtaining a second simulation result based on the revised netlist, and comparing the first simulation result to the second simulation result to determine a leakage-based design impact.

CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT (18347947)

Main Inventor

Huaixin XIAN

Brief explanation

The patent application describes an integrated circuit with a unique structure and circuit layout. Here are the key points:

• The integrated circuit has three main components: a main circuit, a group-one circuit, and a group-two circuit.
• There is a middle active-region structure positioned between the group-one and group-two active-region structures.
• The main circuit includes at least one boundary gate-conductor that intersects the middle active-region structure.
• The group-one circuit has a group-one isolation structure that separates the group-one active-region structure into two parts: one in the group-one circuit and another in a first adjacent circuit.
• Similarly, the group-two circuit has a group-two isolation structure that separates the group-two active-region structure into two parts: one in the group-two circuit and another in a second adjacent circuit.

Abstract

An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

LEAKAGE REDUCTION BETWEEN TWO TRANSISTOR DEVICES ON A SAME CONTINUOUS FIN (18355501)

Main Inventor

Chun-Yen Lin

Brief explanation

The patent application describes a method for fabricating a semiconductor device with improved performance. 

• The method involves removing portions of a substrate to create a continuous fin structure on the surface of the substrate.
• A doping process is then used to increase the concentration of dopants in a specific portion of the fin.
• Gate electrodes are formed over different portions of the fin, with a dummy gate electrode placed in between two other gate electrodes.
• Upper portions of the fin between the gate electrodes and the dummy gate electrode are removed.
• Source/drain regions are then formed between the gate electrodes and the dummy gate electrode.

Abstract

In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin protruding from an upper surface of the substrate. A doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second and third portions of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT (18354423)

Main Inventor

Jung-Chan YANG

Brief explanation

The patent application describes an integrated circuit structure with multiple power rails and sets of conductive structures at different levels.

• The integrated circuit structure includes three power rails extending in one direction.
• There are three sets of conductive structures located at a second level, extending in a different direction.
• Additionally, there are three conductive structures located at a third level, also extending in the same direction as the second set.
• Each conductive structure at the third level overlaps with a corresponding conductive structure from the second set.

Abstract

An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

INTEGRATED CIRCUIT DESIGN USING FUZZY MACHINE LEARNING (18225020)

Main Inventor

Chao Tong

Brief explanation

The patent application describes a system and method for generating place and route (PnR) layouts for integrated circuits based on a received design and floorplans.

• The system receives a functional integrated circuit design and generates multiple PnR layouts.
• The PnR layouts are analyzed using fuzzy logic rules to evaluate their attributes.
• A PnR layout that complies with the fuzzy logic rules and has optimal area utilization is generated.
• The invention aims to improve the efficiency and accuracy of generating PnR layouts for integrated circuits.

Abstract

Systems and methods include receiving a functional integrated circuit design and generating a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and one or more integrated circuit floorplans may be generated. One or more fuzzy logic rules may be applied to analyze attributes associated with each of the generated PnR layouts, and a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules may be generated.

NEW WAS CELL FOR SRAM HIGH-R ISSUE IN ADVANCED TECHNOLOGY NODE (18354824)

Main Inventor

Yangsyu Lin

Brief explanation

The patent application describes a memory device with a memory array consisting of multiple memory cells arranged in rows and columns.

• The memory array also includes write assist cells that are connected to the memory cells.
• Each column in the memory array has at least one write assist cell, which is connected to the memory cells in the same column.
• The purpose of the write assist cells is to enhance the writing process in the memory cells.
• This design allows for improved performance and efficiency in memory operations.

Abstract

A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

CONTROL CIRCUIT, MEMORY SYSTEM AND CONTROL METHOD (18354631)

Main Inventor

Win-San Khwa

Brief explanation

The patent application describes a control circuit, memory system, and control method for controlling memory cells in a memory array.

• The control circuit includes a program controller that programs the electrical characteristics of the memory cells based on the error tolerance of a specific type of data.
• The program controller creates a first electrical characteristic distribution and a second electrical characteristic distribution for the memory cells.
• The first overlapping area between the two distributions is smaller than a predetermined value.
• The purpose of this control circuit is to optimize the programming of memory cells to improve data storage and retrieval efficiency.

Abstract

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

PROBE CARD DEVICE AND CIRCUIT PROTECTION ASSEMBLY THEREOF (17809901)

Main Inventor

Chih-Chieh LIAO

Brief explanation

The patent application describes a probe card device that includes a wiring board, a probe head, and a circuit protection assembly.

• The wiring board has multiple contacts.
• The probe head has a probe holder and multiple conductive probes arranged on it.
• The circuit protection assembly includes an insulation plate, through holes, and self-resetting fusing elements.
• The insulation plate is placed between the wiring board and the probe head.
• The through holes are formed on the insulation plate in an array form.
• The self-resetting fusing elements are placed within the through holes.
• Each self-resetting fusing element is connected to a contact and a conductive probe.
• The purpose of the self-resetting fusing elements is to break down electric currents from the wiring board to the conductive probe.
• The self-resetting fusing elements can reverse the breakdown and restore the electric current flow.

Abstract

A probe card device includes a wiring board provided with a plurality of contacts, a probe head having a probe holder and a plurality of conductive probes arranged on the probe holder, respectively, and a circuit protection assembly including an insulation plate, a plurality of through holes and a plurality of self-resetting fusing elements. The insulation plate is sandwiched between the wiring board and the probe head. The through holes are respectively formed on the insulation plate and arranged in an array form. The self-resetting fusing elements are respectively disposed within the through holes. Each of the self-resetting fusing elements is electrically connected to one of the contacts and one of the conductive probes for reversibly breaking down electric currents from the wiring board to the conductive probe.

REFLECTION MODE PHOTOMASK (18356366)

Main Inventor

Chun-Lang CHEN

Brief explanation

The abstract describes a photomask that is used in reflection mode. 

• The photomask consists of multiple layers on a substrate.
• It includes several absorber stacks, each consisting of an absorber layer and an anti-reflective coating (ARC) layer.
• The material used for the absorber layer can be either tantalum oxynitride or tantalum silicon oxynitride.
• The material used for the ARC layer can be either tantalum nitride or tantalum silicon.

Abstract

A reflection mode photomask includes a multilayer over a substrate. The reflection mode photomask further includes a plurality of absorber stacks over the multilayer. Each absorber stack of the plurality of absorber stacks includes an absorber layer, wherein a material of the absorber layer is selected from the group consisting of tantalum oxynitride and tantalum silicon oxynitride. Each absorber stack of the plurality of absorber stacks further includes an anti-reflective coating (ARC) layer on the absorber layer, wherein a material of the ARC layer is selected from the group consisting of tantalum nitride and tantalum silicon.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME (17736186)

Main Inventor

Meng-Hsiu HSIEH

Brief explanation

- The patent application describes a method for fabricating a semiconductor device.

- The method involves generating a redistribution layer (RDL) layout, which includes multiple redistribution lines. - A first dummy region is determined in the RDL layout based on the redistribution lines. - Multiple first dummy redistribution lines are placed in the first dummy region. - A first modification process is performed to enlarge at least one of the first dummy redistribution lines. - If the area of the enlarged dummy redistribution line exceeds a threshold value, it is determined as a second dummy region in the RDL layout. - Multiple second dummy redistribution lines are then placed in the second dummy region. - Finally, a metal layer is patterned according to the RDL layout after the second dummy redistribution lines are placed in the second dummy region.

Abstract

A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.

WAFER THINNING METHOD HAVING FEEDBACK CONTROL (18356388)

Main Inventor

Yuan-Hsuan CHEN

Brief explanation

The patent application describes a method for thinning a wafer.

• The initial thickness of the wafer is measured.
• A polishing time is calculated based on the initial thickness.
• The wafer is polished for the calculated polishing time to obtain a polished wafer.
• The polished thickness of the polished wafer is measured.
• An etching time is calculated based on the polished thickness.
• The polished wafer is etched for the calculated etching time to obtain an etched wafer.
• The etched wafer has a total thickness variation of less than or equal to 0.15 μm.

Abstract

A method of thinning a wafer includes measuring an initial thickness of the wafer. The method further includes calculating a polishing time using the initial thickness. The method further includes polishing the wafer for a first duration equal to the polishing time to obtain a polished wafer. The method further includes measuring a polished thickness of the polished wafer. The method further includes calculating an etching time using the polished thickness. The method further includes etching the polished wafer for a second duration equal to the etching time to obtain an etched wafer, wherein the wafer has a total thickness variation of less than or equal to 0.15 μm after etching the polished wafer.

WAFER CLEANING METHOD (18351566)

Main Inventor

Kuo-Shu TSENG

Brief explanation

- The patent application describes a method for cleaning contaminants on a wafer, specifically focusing on the backside of the wafer.

- The backside of the wafer is divided into a clear area and an unclear area, with the contaminants located in the unclear area. - The method involves inspecting the backside of the wafer using an inspection device and generating an inspection signal. - A control signal is then generated based on the inspection signal by a process module. - The control signal includes movement information of a brush element, which is determined based on the coordinates of the contaminants obtained from the inspection signal. - A control device is used to control the brush element and guide it along a predetermined path to clean the contaminants on the backside of the wafer.

Abstract

A wafer cleaning method for cleaning contaminants on a wafer is provided, wherein the backside of the wafer has a clear area and an unclear area, and the contaminants are located in the unclear area. The wafer cleaning method includes inspecting the backside of the wafer and generating an inspection signal by an inspection device. The wafer cleaning method includes generating a control signal according to the inspection signal by a process module, wherein the control signal includes movement information of a brush element according to coordinates of the contaminants obtained from the inspection signal. The wafer cleaning method includes controlling the brush element to clean the contaminants on the backside of the wafer according to the control signal by a control device along a predetermined path.

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (17661838)

Main Inventor

Hsuan-Ying PENG

Brief explanation

- The patent application describes a deposition tool that includes a grounding component to improve the yield of semiconductor products.

- The grounding component includes a grounding strap with a deformation region that has a recessed edge to reduce rubbing against a surface of the pumping plate component during operation. - The material properties of the grounding strap are designed to reduce plastic deformation during repeated cycling. - By reducing the amount of particulates dislodged from the pumping plate component, the yield of semiconductor products can be improved. - The frequency of servicing the grounding component can be decreased, resulting in decreased downtime of the deposition tool and increased throughput of semiconductor products.

Abstract

Some implementations described herein provide a deposition tool that includes a grounding component between an edge ring of a substrate stage and a pumping plate component. The grounding component includes a grounding strap having a deformation region. The deformation region includes a recessed edge to reduce a likelihood of the grounding strap rubbing against a surface of the pumping plate component during operation of the deposition tool. Material properties of the grounding strap may reduce a likelihood of plastic deformation of the grounding strap during repeated cycling. In this way, an amount of particulates dislodged from the surface of the pumping plate component may be decreased to improve a yield of semiconductor product fabricated using the deposition tool. Furthermore, a frequency of servicing the grounding component may be decreased to decrease a downtime of the deposition tool and increase a throughput of semiconductor product fabricated using the deposition tool.

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17738182)

Main Inventor

Chih-Hsin YANG

Brief explanation

The patent application describes a method for forming a semiconductor structure. 

• The method involves forming a contact feature over an insulating layer.
• A first passivation layer is then formed over the contact feature.
• The first passivation layer is etched to create a trench that exposes the contact feature.
• An oxide layer is formed over the contact feature, the first passivation layer, and in the trench.
• A first non-conductive structure is formed over the oxide layer.
• The first non-conductive structure is patterned to create a gap.
• A conductive material is filled into the gap to create a first conductive feature.
• The first non-conductive structure and the first conductive feature together form a first bonding structure.
• A carrier substrate is attached to the first bonding structure using a second bonding structure over the carrier substrate.

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18356212)

Main Inventor

Sheng-Chieh Yang

Brief explanation

The patent application describes a semiconductor package that includes a semiconductor device, an encapsulating material, and a redistribution structure.

• The semiconductor device has conductive bumps and a dielectric film encapsulating them.
• The dielectric film is made of an epoxy resin and a filler material.
• The dielectric film isolates the conductive bumps from the encapsulating material.
• The redistribution structure is connected to the conductive bumps.

Abstract

A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.

ISOLATION WITH MULTI-STEP STRUCTURE (18343947)

Main Inventor

Ta-Chun LIN

Brief explanation

The abstract describes a semiconductor device structure that includes a semiconductor substrate with a first well region of a certain conductivity type. It also includes two fin structures protruding from the first well region, with an isolation structure between them. The sidewall surfaces of the fin structures extend from the bottom to the top of the isolation structure.

• Semiconductor device structure with fin structures and isolation structure
• Fin structures protrude from the first well region
• Isolation structure separates the fin structures
• Sidewall surfaces of the fin structures extend from bottom to top of the isolation structure

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Middle-Of-Line Interconnect Structure Having Air Gap And Method Of Fabrication Thereof (18356911)

Main Inventor

Yi-Nien Su

Brief explanation

The patent application describes a new type of interconnect for electronic devices that helps reduce capacitance and resistance. 

• The interconnect structure includes a device-level contact and a ruthenium structure.
• The device-level contact physically connects to an integrated circuit feature.
• The ruthenium structure physically connects to the device-level contact.
• There is an air gap between the sidewalls of the ruthenium structure and the insulator layer.
• The top surface of the ruthenium structure is lower than the top surface of the insulator layer.
• A via in a third insulator layer connects to the ruthenium structure.
• A dummy contact spacer layer separates the first and second insulator layers.

Abstract

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

METHOD OF FABRICATING CONTACT STRUCTURE (17738009)

Main Inventor

Chang-Ting Chung

Brief explanation

The patent application describes a method of fabricating a contact structure in electronic devices. 

• The method involves creating an opening in a dielectric layer and depositing a conductive material layer within the opening and on the dielectric layer.
• The conductive material layer has a bottom section with a smaller thickness and a top section with a larger thickness.
• A first treatment is performed to form an oxide layer on both the bottom and top sections of the conductive material layer.
• A second treatment is then carried out to remove parts of the oxide layer and the conductive material layer.
• After the second treatment, the bottom and top sections of the conductive material layer have equal thickness.

Abstract

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

SYSTEM AND METHOD FOR HIGH SPEED INSPECTION OF SEMICONDUCTOR SUBSTRATES (18223498)

Main Inventor

Sheng He HUANG

Brief explanation

This patent application describes a method for inspecting a semiconductor substrate using light beams.

• A first beam of light is split into multiple second beams of light.
• The second beams of light are transmitted onto a first set of locations on top of the semiconductor substrate.
• The reflected beams of light from the first set of locations are received.
• The received reflected beams of light are detected to generate signals.
• The signals are analyzed to determine if there are any defects at the first set of locations.

Abstract

In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.

METHOD FOR NON-DESTRUCTIVE INSPECTION OF CELL ETCH REDEPOSITION (18352382)

Main Inventor

I-Che Lee

Brief explanation

The patent application is for a method of inspecting cell etch redeposition without causing damage. Here are the key points:

• The method involves capturing a grayscale image of a group of cells on a wafer.
• This image is taken after the etching process that forms the cells.
• The cells are identified in the image to determine non-region of interest (non-ROI) pixels.
• The non-ROI pixels, which correspond to the cells, are subtracted from the image.
• This subtraction reveals the remaining pixels, known as ROI pixels, which represent material on the sidewalls of the cells and in the recesses between them.
• The amount of etch redeposition on the sidewalls and in the recesses is then determined based on the gray levels of the ROI pixels.
• The wafer is then processed based on this score, likely to address any issues with the etch redeposition.

Abstract

Various embodiments of the present disclosure are directed towards a method for nondestructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

PACKAGE AND MANUFACTURING METHOD THEREOF (18355379)

Main Inventor

Yung-Chi Chu

Brief explanation

The patent application describes a package that includes a die, an encapsulant, and a redistribution structure.

• The die is laterally encapsulated by the encapsulant.
• The redistribution structure is placed over the die and the encapsulant.
• The redistribution structure partially exposes the die.
• The top surface of the redistribution structure is slanted downward continuously from an edge of the package towards the interior of the package.

Abstract

A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure partially exposes the die. A top surface of the redistribution structure is slanted downward continuously from an edge of the package toward an interior of the package.

SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER (18352271)

Main Inventor

Sheng-An Kuo

Brief explanation

The patent application describes a semiconductor structure that includes two semiconductor dies stacked on top of each other, with a passivation layer covering the top die. 

• The structure includes a first semiconductor die and a second semiconductor die stacked on top of each other.
• A passivation layer is applied over the second semiconductor die, covering it completely.
• The passivation layer has openings that reveal the pads of the second semiconductor die.
• An anti-arcing pattern is placed on top of the passivation layer.
• Conductive terminals are placed on top of the anti-arcing pattern and are electrically connected to the pads of the second semiconductor die.

Abstract

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE DIE STACKING STRUCTURE (17738032)

Main Inventor

Su-Chun Yang

Brief explanation

The patent application describes a die stacking structure, semiconductor package, and a manufacturing method for the structure.

• The structure includes a first device die and multiple second device dies bonded onto the first die and arranged side-by-side.
• A gap profile modifier is present, which surrounds the bottommost portions of the second device dies. The thickness of the modifier gradually decreases away from the sidewalls of the second dies.
• The second device dies are laterally enclosed by a dielectric material, which also covers the gap profile modifier.
• The purpose of this structure is to provide a compact and efficient arrangement of multiple device dies in a semiconductor package.
• The gradual decrease in thickness of the gap profile modifier helps to optimize the electrical performance and thermal dissipation of the stacked dies.
• The dielectric material provides insulation and protection to the second device dies and the gap profile modifier.
• This innovation can potentially improve the performance and reliability of semiconductor packages with stacked dies.

Abstract

A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.

METHOD OF FABRICATING PACKAGE STRUCTURE (18356227)

Main Inventor

Chih-Hao Chen

Brief explanation

The patent application describes a structure that includes several components: a circuit substrate, a device, a metal layer, a lid, and a thermal interface material layer.

• The device is placed on the circuit substrate and is electrically connected to it.
• The device consists of at least one semiconductor die that is surrounded by an insulating encapsulation.
• A metal layer covers the back surface of the semiconductor die and the insulating encapsulation.
• A lid is positioned on the circuit substrate and is attached to the metal layer through a thermal interface material layer.

Abstract

A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

OVERSIZED VIA AS THROUGH-SUBSTRATE-VIA (TSV) STOP LAYER (18355463)

Main Inventor

Min-Feng Kao

Brief explanation

- The patent application is about an integrated chip structure.

- The structure includes two vias (electrical connections) within a dielectric structure on a substrate. - The first via is smaller in width than the second via and they are laterally separated by the dielectric structure. - An interconnect wire makes contact with the second via and extends past its outermost sidewall. - A through-substrate via (TSV) is positioned over the second via and extends through the substrate. - The TSV has a smaller width than the second via. - The second via's outermost sidewalls are located outside of the TSV.

Abstract

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING (17662366)

Main Inventor

Hsien-Wei CHEN

Brief explanation

- The patent application describes a semiconductor package that is used in high-performance computing.

- The package includes an interposer, which is a component that connects the integrated circuit die to the substrate. - A spacer structure is mounted to the bottom surface of the interposer. - The spacer structure is designed to maintain a clearance between the integrated circuit die and the substrate. - This clearance reduces the likelihood of interference or collision between the die and the substrate, which could cause damage. - By reducing the likelihood of damage, the reliability and yield of the semiconductor package are improved. - The spacer structure also improves the electrical connection between the die and the interposer, increasing its robustness. - Overall, the innovation aims to reduce the likelihood of damage to the die and substrate, while improving the reliability and yield of the semiconductor package.

Abstract

A semiconductor package, which may correspond to a high-performance computing package, includes an interposer over a substrate. A spacer structure is mounted to a bottom surface of the interposer. The spacer structure is configured to maintain a clearance between a bottom surface of an integrated circuit die mounted to the bottom surface of the interposer and a top surface of the substrate to reduce a likelihood of an interference or collision between the integrated circuit die and the substrate. In this way, a likelihood of damage to the integrated circuit die and/or the substrate is reduced. Additionally, a robustness of an electrical connection between the integrated circuit die and the interposer may increase to improve a reliability and/or a yield of the semiconductor package including the spacer structure.

VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE (18353997)

Main Inventor

Te-Hsien Hsieh

Brief explanation

The patent application describes an integrated chip with a conductive structure embedded in a substrate or a dielectric layer.

• The conductive structure is surrounded by a first barrier layer on its sides and bottom, and a second barrier layer on top of the first barrier layer.
• The second barrier layer separates the first barrier layer from the substrate or dielectric layer.
• A second dielectric layer is placed on top of the substrate or dielectric layer.
• A via structure extends through the second dielectric layer and is directly connected to the conductive structure through the first and second barrier layers.

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

PACKAGE HAVING DIFFERENT METAL DENSITIES IN DIFFERENT REGIONS AND MANUFACTURING METHOD THEREOF (18356224)

Main Inventor

Hsien-Wei Chen

Brief explanation

The abstract describes a package that consists of two regions, with one region encircling the other. The package includes two dies, an encapsulant, and an inductor. 

• The first die is located in both regions, while the second die is bonded to the first die and is completely located within the first region.
• The encapsulant surrounds the second die and is present in both regions.
• The inductor is located entirely within the second region.
• The first region has a higher metal density compared to the second region.

Abstract

A package has a first region and a second region encircled by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die is located in both the first region and the second region. The second die is bonded to the first die and is completely located within the first region. The encapsulant laterally encapsulates the second die. The encapsulant is located in both the first region and the second region. The inductor is completely located within the second region. A metal density in the first region is greater than a metal density in the second region.

SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18221787)

Main Inventor

Gerben DOORNBOS

Brief explanation

The patent application describes a semiconductor device that includes a main circuit and a backside power delivery circuit.

• The main circuit is located on the front surface of the substrate.
• The backside power delivery circuit is located on the back surface of the substrate.
• The backside power delivery circuit includes various power supply wirings and a switch.
• The power supply wirings are embedded in a backside insulating layer on the substrate.
• The backside power delivery circuit is connected to the main circuit through a through-silicon via (TSV) passing through the substrate.
• The TSV allows the backside power delivery circuit to supply power to the main circuit.

Abstract

A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME (18224209)

Main Inventor

Wei-Hao Liao

Brief explanation

The patent application describes an interconnect structure used in electronic devices.

• The structure includes a dielectric layer, three conductive features, and a dielectric fill.
• The first conductive feature is located within the dielectric layer.
• The second conductive feature is positioned above the first conductive feature and consists of three layers of conductive material.
• The third conductive feature is located above the dielectric layer.
• The dielectric fill is placed between the second and third conductive features.
• The conductive layers in the second feature have the same width.
• This interconnect structure improves the efficiency and performance of electronic devices.

Abstract

An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

RUTHENIUM OXIDE FILM AND RUTHENIUM LINER FOR LOW-RESISTANCE COPPER INTERCONNECTS IN A DEVICE (18352299)

Main Inventor

Shu-Cheng CHIN

Brief explanation

- The patent application is about using selective ruthenium and selective ruthenium oxide in the manufacturing process of electronic devices.

- These materials are used in the formation of BEOL metallization layers and vias. - The purpose of using selective ruthenium is to achieve low contact resistance and low sheet resistance for the metallization layers and vias. - It also helps in promoting adhesion between different layers and materials in the metallization layers and vias. - Additionally, using selective ruthenium can help reduce or eliminate defects like voids and discontinuities in the metallization layers and vias.

Abstract

Selective ruthenium and selective ruthenium oxide may be used in single damascene processes and/or dual damascene processes to form BEOL metallization layers and vias of an electronic device. A selective ruthenium liner may be formed to achieve a low contact resistance and a low sheet resistance for the BEOL metallization layers and vias, to promote adhesion between the various layers and materials in the BEOL metallization layers and vias, and/or to reduce or eliminate defects (such as voids and discontinuities) in the BEOL metallization layers and vias.

INTEGRATED CHIP HAVING A BURIED POWER RAIL (18347775)

Main Inventor

Marcus Johannes Henricus Van Dal

Brief explanation

The abstract of the patent application describes an integrated chip with specific components and structures. Here is a simplified explanation of the abstract:

• The patent application is about an integrated chip that has a channel structure on a first substrate.
• The chip also includes a gate electrode that is positioned over the channel structure.
• There is a first source/drain structure that is adjacent to the channel structure but is not directly aligned with the gate electrode.
• A conductive structure is present on the first substrate and is located underneath the first source/drain structure.
• A first contact extends from the first source/drain structure to the conductive structure.

In summary, the patent application describes an integrated chip design that includes a specific arrangement of components and structures to achieve certain functionalities.

Abstract

The present disclosure relates to an integrated chip including a channel structure on a first substrate. A gate electrode overlies the channel structure. A first source/drain structure abuts the channel structure and is offset from the gate electrode. A conductive structure is disposed on the first substrate and underlies the first source/drain structure. A first contact extends from the first source/drain structure to the conductive structure.

SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING (17661858)

Main Inventor

Hsien-Wei CHEN

Brief explanation

The patent application describes a semiconductor package for high-performance computing.

• The package includes an integrated circuit die connected to an interposer.
• The interposer has connection structures on its bottom surface.
• The top surface of the interposer has test contact structures connected to the integrated circuit die.
• These test contact structures can be probed to test the quality and reliability of the integrated circuit die and the functionality of the interposer traces.
• By testing the integrated circuit die and interposer traces through the test contact structures, the connection structures are not probed, reducing the risk of damage to the solder joints between the connection structures and the substrate.
• This improves the reliability and quality of the semiconductor package.

Abstract

A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures. In this way, damage to the connection structures, due to probing, may be avoided to improve a reliability and/or a quality of solder joints between the connection structures and a substrate to which the interposer is subsequently mounted.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE (17737998)

Main Inventor

Wei-Ming Wang

Brief explanation

The patent application describes a semiconductor package with multiple dies and an interlink structure. 

• The package includes a substrate, a first die, and a second die.
• The first die is thicker than the second die.
• A resistant layer is placed on both dies, covering them completely.
• An encapsulant is applied on top of the resistant layer, surrounding the first and second dies.
• The interlink structure is positioned above the dies and embedded in the encapsulant.
• The interlink structure is electrically connected to both the first and second dies.
• The interlink structure consists of a first via portion connected to the first die, a second via portion connected to the second die, and a routing line portion connecting the two via portions.
• The first via portion is shorter than the second via portion.

Abstract

A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF (18354633)

Main Inventor

Tsung-Fu Tsai

Brief explanation

The patent application describes a package structure for electronic devices.

• The structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure.
• The redistribution circuit structure has dielectric layers.
• The wiring substrate is placed on top of the redistribution circuit structure.
• The insulating encapsulation surrounds the wiring substrate.
• The reinforcement structure consists of reinforcement pattern layers and reinforcement vias.
• The reinforcement pattern layers and dielectric layers are stacked alternately.
• The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers.
• At least one of the reinforcement pattern layers is embedded in the insulating encapsulation.
• The reinforcement structure is electrically floating, meaning it is not connected to any electrical circuit.

Abstract

A package structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. At least one of the reinforcement pattern layers is embedded in the insulating encapsulation. The reinforcement structure is electrically floating.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (17738016)

Main Inventor

Wei-Huan Fu

Brief explanation

The patent application describes a semiconductor device with multiple layers and pads for electrical connections.

• The device layer is placed on a substrate and has a top metal feature.
• A first passivation layer is added on top of the device layer.
• An aluminum pad is inserted through the first passivation layer and connected to the top metal feature.
• A second passivation layer is then applied over the aluminum pad.
• An under-ball metallurgy (UBM) pad is inserted through the second passivation layer and connected to the aluminum pad.
• Finally, a connector is placed on top of the UBM pad.
• The aluminum pad has a greater angle between its sidewall and bottom compared to the UBM pad.

Abstract

A semiconductor device includes a device layer, a first passivation layer, an aluminum pad, a second passivation layer, an under-ball metallurgy (UBM) pad and a connector. The device layer is disposed over a substrate, wherein the device layer includes a top metal feature. The first passivation layer is disposed over the device layer. The aluminum pad penetrates through the first passivation layer and is electrically connected to the top metal feature. The second passivation layer is disposed over the aluminum pad. The UBM pad penetrates through the second passivation layer and is electrically connected to the aluminum pad. The connector is disposed over the UBM pad. In some embodiments, a first included angle between a sidewall and a bottom of the aluminum pad is greater than a second included angle between a sidewall and a bottom of the UBM pad.

METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE (18354668)

Main Inventor

Chia-Kuei Hsu

Brief explanation

The patent application describes a redistribution structure that includes multiple layers of dielectric material and a pad pattern.

• The structure consists of a first dielectric layer, a pad pattern, and a second dielectric layer.
• The pad pattern is placed on top of the first dielectric layer and consists of a pad portion and a peripheral portion.
• The pad portion is embedded within the first dielectric layer, with its lower surface being at the same level as the lower surface of the first dielectric layer.
• The peripheral portion surrounds the pad portion.
• The second dielectric layer is then placed on top of the pad pattern.
• The second dielectric layer includes extending portions that go through the peripheral portion of the pad pattern.
• The extending portions provide additional connectivity and routing options within the redistribution structure.

Abstract

A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18352270)

Main Inventor

Min-Feng Kao

Brief explanation

The patent application describes a semiconductor structure and a method for manufacturing it.

• The semiconductor structure consists of three tiers: top, middle, and bottom.
• The bottom tier includes a first interconnect structure and a first front-side bonding structure.
• The middle tier is placed between the top and bottom tiers and is electrically connected to them.
• The middle tier includes a second interconnect structure, a second front-side bonding structure, and a back-side bonding structure.
• The second front-side bonding structure has a bonding feature that includes a first bonding via, a first bonding contact, and a barrier layer interface.
• The first bonding via is in contact with the second interconnect structure.
• The first bonding contact overlies the first bonding via.
• The barrier layer interface is between the bottom of the first bonding contact and the top of the first bonding via.
• The manufacturing method for the semiconductor structure is not described in detail in the abstract.

Abstract

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME (18354614)

Main Inventor

Shih-Wei Chen

Brief explanation

The patent application describes a semiconductor package with a redistribution structure, semiconductor devices, a heat dissipation component, and an encapsulating material.

• The semiconductor devices are placed on and connected to the redistribution structure.
• The heat dissipation component has a concave portion that receives the semiconductor devices and an extending portion that contacts the redistribution structure.
• The concave portion of the heat dissipation component directly contacts the semiconductor devices.
• The encapsulating material covers the redistribution structure, fills the concave portion, and encapsulates the semiconductor devices.

Abstract

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME (18224065)

Main Inventor

Shin-Yi YANG

Brief explanation

- The patent application describes an integrated circuit die with edge interconnect features.

- These edge interconnect features are conductive lines that extend through sealing rings and are exposed on the edge surfaces of the integrated circuit die. - The purpose of these edge interconnect features is to connect with other integrated circuit dies without the need for an interposer. - The semiconductor device can include multiple integrated circuit dies with edge interconnect features, which are connected through inter-chip connectors formed between them. - The inter-chip connectors can be formed using a selective bumping process during packaging.

Abstract

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

IN-MEMORY COMPUTING CIRCUIT AND FABRICATION METHOD THEREOF (17736971)

Main Inventor

Hidehiro Fujiwara

Brief explanation

The patent application describes an in-memory computing circuit that includes a core die, conductive pillars, and memory dies.

• The circuit is designed to perform computing operations using memory dies that are connected to the core die through conductive pillars.
• The memory dies are capable of implementing computing operations.
• At least one of the memory dies is located on the bottommost memory die.
• The core die sends input data to the memory dies through a common input terminal.

Abstract

An in-memory computing circuit is provided. The in-memory computing circuit includes a core die, a plurality of conductive pillars, and a plurality of memory dies. The plurality of memory dies are coupled to the core die through the plurality of conductive pillars and are configured to implement computing operation. The plurality of memory dies includes at least one of the memory dies disposed on a bottommost memory die of the plurality of memory dies. The plurality of memory dies receives an input data from the core die through a common input terminal of the core die.

HYBRID BOND PAD STRUCTURE (18355524)

Main Inventor

Sin-Yao Huang

Brief explanation

The patent application is about an integrated chip structure that includes two tiers of integrated chips.

• The first tier of the integrated chip is connected to the second tier through a bonding interface.
• The second tier has a second insulating structure and a second plurality of conductors.
• A conductive pad is connected to the second plurality of conductors and has a conductive surface.
• The conductive surface is located on the side of the second semiconductor body facing away from the first semiconductor body.
• The bonding interface includes conductive and insulating regions.
• The conductive regions are located outside of the bottom surface of the conductive pad.

Abstract

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.

STACKING STRUCTURE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME (18357137)

Main Inventor

Ming-Fa Chen

Brief explanation

The abstract describes a package structure that includes multiple stacked die units and an insulating encapsulant. Each stacked die unit consists of a semiconductor die and a bonding chip. The semiconductor die has bonding pads, while the bonding chip has bonding structures. The bonding structures are connected to the bonding pads using hybrid bonding. The stacked die units are then encapsulated with an insulating material.

• Package structure with stacked die units and insulating encapsulant
• Stacked die units consist of semiconductor die and bonding chip
• Semiconductor die has bonding pads
• Bonding chip has bonding structures
• Bonding structures are connected to bonding pads using hybrid bonding
• Stacked die units are encapsulated with insulating material

Abstract

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

INTEGRATED CIRCUIT DEVICE AND METHOD (18355273)

Main Inventor

Wei-Ren CHEN

Brief explanation

The patent application describes an integrated circuit (IC) device that includes a substrate, active regions, gate regions, and input/output (IO) patterns.

• The IC device has a substrate, which is a base material for the circuit.
• The active regions are areas on the substrate that perform specific functions.
• The gate regions extend across the active regions and control their operation.
• The IO patterns are designed to connect the active regions and gate regions to other circuitry.
• The IO patterns are positioned obliquely to the active regions or gate regions, meaning they are not aligned in a straight line.
• This configuration allows for more efficient electrical coupling between the active regions, gate regions, and other circuitry.
• The innovation in this patent application is the oblique positioning of the IO patterns, which improves the performance and functionality of the IC device.

Abstract

An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME (18225114)

Main Inventor

Ta-Chun LIN

Brief explanation

The patent application describes a semiconductor structure with two semiconductor devices formed over a substrate.

• The first semiconductor device includes a first source/drain feature, a first gate structure, a first conductive feature, and a first insulation layer.
• The first insulation layer contains a first contact etching stop layer (CESL) in contact with the first source/drain feature.
• The second semiconductor device includes a second source/drain feature, a second gate structure, a second conductive feature, and a second insulation layer.
• The second insulation layer contains a second CESL in contact with the second source/drain feature.
• The thickness of the first CESL is smaller than the thickness of the second CESL.

Abstract

A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature. The semiconductor structure includes a second semiconductor device formed over the substrate, including a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature, the second insulation layer comprises a second CESL in contact with the second source/drain feature, wherein a thickness of the first CESL is less than a thickness of the second CESL.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18224000)

Main Inventor

Wei-Yuan LU

Brief explanation

The patent application describes a method of manufacturing a semiconductor device.

• The method involves forming an interlayer dielectric (ILD) layer over an underlying structure.
• The underlying structure includes a gate structure and a first source/drain epitaxial layer.
• A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and the upper portion of the first source/drain epitaxial layer.
• A second source/drain epitaxial layer is then formed over the etched first source/drain epitaxial layer.
• Finally, a conductive material is formed over the second source/drain epitaxial layer.

Abstract

In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME (18224487)

Main Inventor

Shun-Jang LIAO

Brief explanation

The patent application describes a semiconductor device that includes two types of field effect transistors (FETs) with different threshold voltages. The device has a first-type-channel FET with a smaller threshold voltage than a second first-type-channel FET. 

• The semiconductor device includes first-type-channel FETs with different threshold voltages.
• The first-type-channel FETs have different gate structures, with the first FET having a first gate structure and the second FET having a second gate structure.
• The first gate structure includes a first work function adjustment material (WFM) layer, while the second gate structure includes a second WFM layer.
• The thickness and material of the WFM layers may be different from each other.

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18348531)

Main Inventor

Kuo-Pi TSENG

Brief explanation

The patent application describes a device that includes various components such as a substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a bottom dielectric structure.

• The device has a substrate, which serves as a base for the other components.
• A channel layer is placed on top of the substrate.
• A gate structure is positioned across the channel layer, controlling the flow of current.
• There are two source/drain epitaxial structures, located on opposite sides of the channel layer and connected to it.
• A bottom dielectric structure is situated between one of the source/drain epitaxial structures and the substrate.
• In a cross-sectional view, the maximum width of the first source/drain epitaxial structure is equal to or greater than the maximum width of the bottom dielectric structure.

Abstract

A device includes a substrate, a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer and are connected to the channel layer. The bottom dielectric structure is between the first source/drain epitaxial structure and the substrate. A maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view.

IMAGE SENSOR WITH SHALLOW TRENCH EDGE DOPING (18342877)

Main Inventor

Yueh-Chuan Lee

Brief explanation

The present disclosure is about an integrated chip that has a gate structure on a substrate.

• Integrated chip with gate structure on a substrate

The substrate contains a doped region.

• Substrate with doped region

One or more dielectric materials are present within a recess formed by the substrate's surfaces.

• Dielectric materials within a recess formed by the substrate

The doped region is located laterally between the gate structure and the recess.

• Doped region between gate structure and recess

Within the recess, there is a doped epitaxial material that is asymmetric about a vertical line passing through its lateral center.

• Asymmetric doped epitaxial material within the recess

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a gate structure on a substrate. A doped region is within the substrate. One or more dielectric materials are within a recess formed by one or more surfaces of the substrate. The doped region is laterally between the gate structure and the recess. A doped epitaxial material is within the recess and between the one or more dielectric materials and the doped region. The doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material.

IMAGE SENSOR AND METHOD OF FORMING THE SAME (17738031)

Main Inventor

Chun-Liang Lu

Brief explanation

The abstract describes an image sensor and a method of forming it.

• The image sensor includes a first substrate with two surfaces.
• There are multiple photodetectors placed in the first substrate.
• On the second surface of the first substrate, there are multiple color filters corresponding to the photodetectors.
• The color filters are made up of PIN diodes.
• The PIN diodes are designed to absorb light of different wavelength ranges by applying different bias voltages.

Abstract

Provided is an image sensor and a method of forming the same. The image sensor includes a first substrate having a first surface and a second surface opposite to each other; a plurality of photodetectors, disposed in the first substrate; and a plurality of color filters, disposed on the second surface of the first substrate and respectively corresponding to the plurality of photodetectors. The plurality of color filters are composed of a plurality of PIN diodes, and the plurality of PIN diodes are configured to absorb light of different wavelength ranges by applying different bias voltages.

IMAGE SENSOR WITH OVERLAP OF BACKSIDE TRENCH ISOLATION STRUCTURE AND VERTICAL TRANSFER GATE (18355481)

Main Inventor

Feng-Chi Hung

Brief explanation

The patent application is for an image sensor device.

• The device includes a photodetector and a transfer transistor.
• The transfer transistor has a transfer gate that extends over the frontside of the semiconductor substrate.
• The transfer gate also has a vertical portion that extends to a certain depth below the frontside of the substrate.
• A gate dielectric separates the transfer gate from the substrate.
• The device also includes a backside trench isolation structure that surrounds the photodetector.
• The backside trench isolation structure extends from the backside of the substrate to a depth below the frontside.
• The depth of the backside trench isolation structure is less than the depth of the vertical portion of the transfer transistor.
• This allows for a vertical overlap between the lowermost portion of the transfer transistor and the uppermost portion of the backside trench isolation structure.

Abstract

Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

BAND-PASS FILTER FOR STACKED SENSOR (18353266)

Main Inventor

Cheng Yu Huang

Brief explanation

- The patent application describes an integrated chip structure that includes two image sensor elements, each capable of generating electrical signals from different ranges of wavelengths.

- A band-pass filter is formed over one of the image sensor elements using a series of deposition processes. - The band-pass filter consists of alternating layers of two different materials with different refractive indices. - The first image sensor element is then bonded to the band-pass filter. - The purpose of the band-pass filter is to selectively allow certain wavelengths of electromagnetic radiation to pass through to the image sensor element, while blocking others. - This integrated chip structure could potentially be used in various applications that require the detection and analysis of electromagnetic radiation within specific wavelength ranges.

Abstract

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes forming a first image sensor element within a first substrate and a second image sensor element within a second substrate. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths and the second image sensor element is configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths. A plurality of deposition processes are performed to form a band-pass filter over the second substrate. The band-pass filter has a plurality of alternating layers of a first material having a first refractive index and a second material having a second refractive index that is less than the first refractive index. The first substrate is bonded to the band-pass filter.

CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS (18356694)

Main Inventor

Po-Chun Liu

Brief explanation

The patent application describes a method for forming a semiconductor device. Here are the key points:

• The method involves etching a substrate to create a recess on its surface.
• An epitaxial material is then formed within the recess.
• A capping structure is formed on top of the epitaxial material.
• A capping layer is added, extending beyond the outermost sidewall of the capping structure.
• Dopants are implanted into the epitaxial material, creating a first doped region with one type of doping and a second doped region with another type of doping.

Abstract

In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.

BACKSIDE DEEP TRENCH ISOLATION (BDTI) STRUCTURE FOR CMOS IMAGE SENSOR (17882869)

Main Inventor

Hsin-Hung Chen

Brief explanation

- The patent application describes a method for forming an image sensor and its associated device structure.

- A backside deep trench isolation (BDTI) structure is created in a substrate to separate multiple pixel regions. - The BDTI structure encloses several photodiodes and consists of two components: a first component located at the intersection of the pixel regions and a second component located at the remaining peripheries of the pixel regions. - The first BDTI component has a smaller depth from the backside of the substrate compared to the second BDTI component. - The purpose of the BDTI structure is to provide isolation between the pixel regions and enhance the performance of the image sensor.

Abstract

In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A backside deep trench isolation (BDTI) structure is formed in a substrate separating a plurality of pixel regions. The BDTI structure encloses a plurality of photodiodes and comprising a first BDTI component arranged at a crossroad of the plurality of pixel regions and a second BDTI component arranged at remaining peripheries of the plurality of pixel regions. The first BDTI component has a first depth from a backside of the substrate smaller than a second depth of the second BDTI component.

SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT (18353307)

Main Inventor

Chi-Cheng CHEN

Brief explanation

The patent application describes a semiconductor device structure that includes a substrate, a magnetic element, an isolation element, and a conductive feature.

• The semiconductor device structure consists of multiple components.
• It includes a substrate, which serves as the foundation for the device.
• The structure also includes a magnetic element that is positioned over the substrate.
• An isolation element is present, which partially covers the magnetic element.
• The isolation element helps to separate and protect the magnetic element.
• Additionally, a conductive feature is placed over the isolation element.
• The conductive feature is designed to facilitate the flow of electrical current.
• The combination of these elements forms the semiconductor device structure.

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.

INTEGRATED CHIP INDUCTOR STRUCTURE (18354842)

Main Inventor

Hung-Wen Hsu

Brief explanation

The patent application is about an inductor structure that includes a magnetic structure and a pattern enhancement layer.

• The inductor structure has an etch stop layer, an interconnect structure, and a substrate.
• The magnetic structure is made up of multiple layers and is placed over the etch stop layer.
• The bottommost layer of the magnetic structure is wider than the topmost layer.
• There are two parallel conductive wires that extend over the magnetic structure.
• The magnetic structure is designed to modify the magnetic fields generated by the conductive wires.
• A pattern enhancement layer is placed between the bottommost layer of the magnetic structure and the etch stop layer.
• The pattern enhancement layer has a certain thickness, while the bottommost layer of the magnetic structure has a smaller thickness.

Abstract

The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17662571)

Main Inventor

Min-Ying TSAI

Brief explanation

The abstract describes a semiconductor device and methods of formation that include a photodiode device and a metal-insulator-metal deep-trench capacitor. The capacitor includes an amorphous material layer that helps reduce leakage and improve the performance of the device.

• The semiconductor device includes a photodiode device and a metal-insulator-metal deep-trench capacitor.
• The deep-trench capacitor has an amorphous material layer between the insulator layer stack and the capacitor bottom metal layer.
• The amorphous material has a bandgap energy level that reduces electron tunneling and improves the device's lag performance.
• The amorphous material helps overcome leakage issues associated with grain boundaries, crystal defects, and interfaces in the insulator layer stack.

Abstract

Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include a photodiode device electrically connected to a metal-insulator-metal deep-trench capacitor. The metal-insulator-metal deep-trench capacitor includes a layer of an amorphous material between an insulator layer stack of the deep-trench capacitor structure and a capacitor bottom metal layer of the metal-insulator-metal deep-trench capacitor. The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the capacitor bottom metal electrode layer to the insulator layer stack. In this way, leakage associated with grain boundaries, crystal defects, and interfaces of a bottom layer of the insulator layer stack may be overcome to improve a lag performance of the semiconductor device including the metal-insulator-metal deep-trench capacitor.

GATE AIR SPACER PROTECTION DURING SOURCE/DRAIN VIA HOLE ETCHING (18355796)

Main Inventor

Kuo-Chiang Tsai

Brief explanation

The patent application describes a semiconductor device with a gate, source/drain, and conductive contact.

• Gate is a component that controls the flow of electricity in the device.
• Source/drain is a region in the substrate where current enters or exits the device.
• Conductive contact is a structure that allows for electrical connection to the source/drain.
• An air spacer is placed between the gate and the conductive contact.
• The air spacer helps to improve the performance and efficiency of the device.
• A first component is placed over the gate, which could be another layer or structure.
• A second component is placed over the air spacer, which is different from the first component.
• The second component could be a different material or have a different function.
• This arrangement of components allows for improved functionality and performance of the semiconductor device.

Abstract

A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component.

SOURCE/DRAIN LEAKAGE PREVENTION (17848701)

Main Inventor

Che-Lun Chang

Brief explanation

The patent application describes a method for forming multi-gate transistor structures. Here are the key points:

• The method involves creating a fin-shaped structure on a substrate, consisting of channel layers separated by sacrificial layers.
• The fin-shaped structure is recessed to create a source/drain recess.
• The sidewalls of the sacrificial layers are further recessed to form inner spacer recesses.
• A dielectric layer is deposited over the substrate and inner spacer recesses, followed by a polymer layer.
• The polymer and dielectric layers are etched back to form inner spacer features in the recesses and an inner spacer layer on the substrate.
• Multiple epitaxial layers are then deposited from the sidewalls of the channel layers to create a source/drain feature in the recess.
• The source/drain feature and inner spacer layer together define a gap.

Overall, this method allows for the formation of multi-gate transistor structures with improved performance and efficiency.

Abstract

Multi-gate transistor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a fin-shaped structure over a substrate and including channel layers interleaved by sacrificial layers, recessing the fin-shaped structure to form a source/drain recess, recessing the sidewalls of the sacrificial layers to form inner spacer recesses, depositing a dielectric layer over the substrate and the inner spacer recesses, depositing a polymer layer over the dielectric layer, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate, and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess. The source/drain feature and the inner spacer layer define a gap.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE (18352249)

Main Inventor

Yi-Tse Hung

Brief explanation

The patent application describes a semiconductor device and a method for manufacturing it.

• The device includes a heat transfer layer, a channel material layer, a gate structure, and source and drain terminals.
• The heat transfer layer is placed on a substrate.
• The channel material layer has two surfaces, with the first surface in contact with the heat transfer layer.
• The gate structure is positioned above the channel material layer.
• The source and drain terminals are in contact with the channel material layer and located on opposite sides of the gate structure.

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17739149)

Main Inventor

Chih-Teng LIAO

Brief explanation

The patent application describes a semiconductor device structure and methods of forming it.

• The structure includes two source/drain regions and an interlayer dielectric layer between them.
• There is a conductive feature in the interlayer dielectric layer, which is connected to the first source/drain region.
• The conductive feature has a first portion and a second portion that form an angle less than 180 degrees.
• The purpose of this structure is not explicitly mentioned in the abstract.

Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain region, a second source/drain region adjacent the first source/drain region, an interlayer dielectric layer disposed between the first source/drain region and the second source/drain region, and a conductive feature disposed in the interlayer dielectric layer between the first source/drain region and the second source/drain region. The conductive feature includes a first portion and a second portion extending from the first portion, and an angle is formed between the first portion and the second portion. The angle is less than about 180 degrees. The conductive feature is electrically connected to the first source/drain region.

ETCH PROFILE CONTROL OF VIA OPENING (18352640)

Main Inventor

Te-Chih HSIUNG

Brief explanation

The patent application describes a device that includes a transistor with a source/drain contact, an etch stop layer, an interlayer dielectric (ILD) layer, and a source/drain via.

• The device has a source/drain contact that is located over a source/drain region of a transistor.
• An etch stop layer is positioned above the source/drain contact.
• An interlayer dielectric (ILD) layer is placed above the etch stop layer.
• A source/drain via extends through the ILD layer and the etch stop layer to connect with the source/drain contact.
• The etch stop layer has an oxidized region that is in contact with the source/drain via.
• The oxidized region is separated from the source/drain contact.

Abstract

A device comprises a source/drain contact over a source/drain region of a transistor, an etch stop layer above the source/drain contact, an interlayer dielectric (ILD) layer above the etch stop layer, and a source/drain via extending through the ILD layer and the etch stop layer to the source/drain contact. The etch stop layer has an oxidized region in contact with the source/drain via and separated from the source/drain contact.

THICKER CORNER OF A GATE DIELECTRIC STRUCTURE AROUND A RECESSED GATE ELECTRODE FOR AN MV DEVICE (18355549)

Main Inventor

Yi-Huan Chen

Brief explanation

The patent application describes a semiconductor device with a well region, source and drain regions, and a gate electrode.

• The device includes a substrate with a well region, and source and drain regions arranged within the substrate.
• A gate electrode is positioned over the well region, extending between the source and drain regions.
• A trench isolation structure surrounds the source region, drain region, and gate electrode.
• A gate dielectric structure separates the gate electrode from the well region, source and drain regions, and trench isolation structure.
• The gate electrode has a central portion and a corner portion, with the corner portion being thicker than the central portion.

Abstract

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (18357163)

Main Inventor

Bo-Feng Young

Brief explanation

The patent application describes a semiconductor device and a method of forming it.

• The device includes a substrate, semiconductor nanosheets, a bottom dielectric layer, and a gate stack.
• The substrate has at least one fin.
• The semiconductor nanosheets are stacked on the fin.
• The bottom dielectric layer is vertically placed between the fin and the nanosheets.
• The gate stack wraps around the nanosheets.
• The projected area of the gate stack on the top surface of the substrate is within the projected area of the bottom dielectric layer on the top surface of the substrate.

Abstract

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is vertically disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. An area of the gate stack projected on a top surface of the substrate is within an area of the bottom dielectric layer projected on the top surface of the substrate.

SEMICONDUCTOR DEVICE AND METHODS OF FORMATION (17662185)

Main Inventor

Hsu Ming HSIAO

Brief explanation

- This patent application describes techniques and semiconductor devices for including a dielectric region in a nanostructure transistor.

- The dielectric region, which could be an air gap, is located between dielectric spacer layers along the sidewall of a metal gate structure. - The dielectric region is formed using a temporary spacer layer made of silicon germanium material. - The temporary spacer layer can be selectively removed without causing damage to the dielectric spacer layers, metal gate structure, or other parts of the nanostructure transistor.

Abstract

Some implementations described herein provide techniques and semiconductor devices in which a dielectric region is included in a nanostructure transistor. The dielectric region, which may correspond to an air gap, may be located between dielectric spacer layers located along a sidewall of a metal gate structure. Techniques to form the dielectric region may include using a temporary spacer layer between the dielectric spacer layers during manufacturing of the nanostructure transistor. The temporary spacer layer may include a silicon germanium material having a reaction mechanism that allows the temporary spacer layer to be selectively removed without causing damage to the dielectric spacer layers, the metal gate structure, or other portions of the nanostructure transistor.

REPLACEMENT SIDEWALL SPACERS (17662126)

Main Inventor

Chang-Ta Chen

Brief explanation

The patent application describes a device with a replacement spacer structure and a method for forming such a structure. 

• The method involves forming an initial spacer structure with a specific etch rate for a chosen etchant.
• A portion of the initial spacer structure is then removed, leaving behind a remaining portion.
• A replacement spacer structure is formed adjacent to the remaining portion of the initial spacer structure, creating a combined spacer structure.
• The combined spacer structure has an intermediate etch rate for the chosen etchant, which is lower than the initial etch rate.
• Finally, the combined spacer structure is etched with the chosen etchant to form a final spacer structure.

Abstract

Provided is a device with a replacement spacer structure and a method for forming such a structure. The method includes forming an initial spacer structure, wherein the initial spacer structure has an initial etch rate for a selected etchant. The method further includes removing a portion of the initial spacer structure, wherein a remaining portion of the initial spacer structure is not removed. Also, the method includes forming a replacement spacer structure adjacent to the remaining portion of the initial spacer structure to form a combined spacer structure, wherein the combined spacer structure has an intermediate etch rate for the selected etchant that is less than the initial etch rate for a selected etchant. Further, the method includes etching the combined spacer structure with the selected etchant to form a final spacer structure.

SEMICONDUCTOR DEVICE HAVING NANOSTRUCTURE TRANSISTOR AND METHODS OF FABRICATION THEREOF (17739078)

Main Inventor

Wen-Kai LIN

Brief explanation

- The patent application describes a method for forming a semiconductor device structure.

- The method involves creating a fin structure by stacking alternating layers of first and second semiconductors. - Edge portions of the second semiconductor layers are removed to create cavities between the first semiconductor layers. - A passivation layer is selectively formed on the sidewalls of the first semiconductor layers. - A dielectric spacer is formed on the sidewalls of the second semiconductor layers and fills in the cavities, exposing the passivation layer. - The passivation layer is then removed. - An epitaxial source/drain feature is formed, making contact with both the first semiconductor layers and the dielectric spacers.

Abstract

Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.

BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FORMING THE SAME (17737003)

Main Inventor

Chun-Tsung KUO

Brief explanation

- The abstract describes a patent application for a Bipolar Junction Transistor (BJT) and methods of forming it.

- The BJT includes a collector region, lower base structure, first and second dielectric layers, upper base structure, emitter region, and sidewall spacer structure. - The first dielectric layer is made of a first oxide, the second dielectric layer is made of a second oxide, and the two oxides have different densities. - The upper base structure is placed on top of the second dielectric layer and the lower base structure. - The emitter region is located on the lower base structure. - The sidewall spacer structure, which separates the emitter region and the upper base structure, is made of a material different from the first and second dielectric layers.

Abstract

A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

CAP STRUCTURE COUPLED TO SOURCE TO REDUCE SATURATION CURRENT IN HEMT DEVICE (18348421)

Main Inventor

Ming-Cheng Lin

Brief explanation

The patent application describes a method of creating a high electron mobility transistor (HEMT) device. Here are the key points:

• The method starts by applying a protective layer over a substrate.
• Within this protective layer, contacts for the source and drain are formed.
• A portion of the protective layer is then removed to create a cavity.
• The cavity is formed by the sidewalls of the protective layer and the sidewall of the source contact.
• A gate structure is then created within the protective layer, positioned between the drain contact and the cavity.
• Finally, a cap structure is formed within the cavity.

Overall, this method allows for the creation of a HEMT device with specific structures and configurations that can enhance its performance.

Abstract

In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

TRANSISTOR STRUCTURE HAVING IMPROVED ELECTRODE CONDUCTANCE AND METHOD FOR MANUFACTURING THE SAME (17737504)

Main Inventor

Ming-Yen CHUANG

Brief explanation

The abstract describes a semiconductor device with a transistor structure on a substrate.

• The transistor structure includes a channel region and a source/drain electrode.
• The channel region has a lower channel portion and multiple upper channel portions.
• The upper channel portions protrude into the source/drain electrode, creating an uneven interface.
• The purpose of this design is not explicitly stated in the abstract.

Abstract

A semiconductor device includes a substrate and a transistor structure disposed on the substrate. The transistor structure includes a channel region and a source/drain electrode disposed on the channel region. The channel region includes a lower channel portion and a plurality of upper channel portions protruding from the lower channel portion into the source/drain electrode to form an uneven interface between the channel region and the source/drain electrode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18352230)

Main Inventor

Chao-Ching Cheng

Brief explanation

The patent application describes a semiconductor device with several components: a substrate, a poly-material pattern, a conductive element, a semiconductor layer, and a gate structure.

• The poly-material pattern is located on top of the substrate and extends outward. It consists of an active portion and a poly-material portion that is connected to the active portion.
• The conductive element is positioned on the substrate and includes the poly-material portion of the poly-material pattern. It also has a metallic conductive portion that covers either the top surface or the sidewall of the poly-material portion.
• The semiconductor layer is placed on top of the substrate and covers both the active portion of the poly-material pattern and the conductive element.
• The gate structure is located on top of the semiconductor layer and is positioned within the active portion of the poly-material pattern.

Abstract

A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

DOUBLE-SIDED STACKED DTC STRUCTURE (18353246)

Main Inventor

Ming Chyi Liu

Brief explanation

The patent application describes an integrated circuit (IC) design that includes multiple layers and structures for improved performance and functionality.

• The IC includes a first insulating layer with a metal interconnect structure and a bottom die.
• A substrate is placed above the first insulating layer.
• A second metal interconnect structure is positioned above the substrate.
• A through-substrate via (TSV) directly connects the first and second metal interconnect structures, allowing for efficient communication between them.
• The IC also features a stacked deep trench capacitor (DTC) structure within the substrate.
• The DTC structure consists of two sets of trenches extending from opposite sides of the substrate.
• These trenches provide additional capacitance, which is crucial for storing and supplying electrical energy in the IC.
• The design aims to enhance the performance and efficiency of the IC by optimizing the interconnectivity and capacitance within the circuit.

Abstract

In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.

CALIBRATION SYSTEM OF CANCELING EFFECT OF PHASE NOISE AND ANALOG-TO-DIGITAL CONVERTING DEVICE COMPRISING THE SAME (18052204)

Main Inventor

Ting-Hao WANG

Brief explanation

The patent application describes a calibration system that includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit, and a first calculation circuit.

• The jitter-capturing ADC samples a clock signal using an operating clock signal to generate a first quantized output.
• The calibration value generating circuit receives the first quantized output and a second quantized output from a to-be-calibrated ADC to generate a calibration value.
• The operating clock signal drives the to-be-calibrated ADC for sampling, and the calibration value is related to the phase noise of the operating clock signal.
• The first calculation circuit subtracts the calibration value from the second quantized output to generate a third quantized output.

Abstract

A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

PHOTOSENSING PIXEL INCLUDING SELF-ALIGNED LIGHT SHIELDING LAYER (17739387)

Main Inventor

Yueh-Chuan LEE

Brief explanation

- The patent application describes a method for creating a light-shielding layer to block light from reaching a light-sensitive storage region in a semiconductor substrate.

- The light-sensitive storage region is used to store electric charges. - A storage gate feature, consisting of a polysilicon gate electrode, is formed over the light-sensitive storage region. - A metal layer is then formed over the storage gate feature. - A silicidation process is performed to convert a portion of the metal layer in contact with the polysilicon gate electrode into a silicide light-shielding layer. - A thermal process is then conducted to promote lateral growth of the silicide light-shielding layer, causing it to extend and cover the lateral surface of the storage gate feature. - The temperature used in the thermal process is higher than that of the silicidation process.

Abstract

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

APPARATUS AND METHOD FOR GENERATING EXTREME ULTRAVIOLET RADIATION (18224005)

Main Inventor

Wei-Chih LAI

Brief explanation

The abstract describes a target droplet source for an extreme ultraviolet (EUV) source. This source includes a droplet generator that produces target droplets of a specific material. The droplet generator has a nozzle that supplies the target droplets within a chamber. Additionally, there is a sleeve located in the chamber, which guides the target droplets along a specific path.

• The patent application is for a target droplet source used in extreme ultraviolet (EUV) sources.
• The source includes a droplet generator that produces target droplets made of a specific material.
• The droplet generator has a nozzle that supplies the target droplets into a chamber.
• A sleeve is placed in the chamber, providing a path for the target droplets.
• The sleeve helps guide the target droplets along a specific trajectory within the chamber.

Abstract

A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME (18352267)

Main Inventor

Jian-Ting Chen

Brief explanation

The patent application describes a semiconductor package assembly that includes a circuit board, a heat dissipating element, and a semiconductor device.

• The circuit board has a conductive pattern.
• The heat dissipating element is placed on the circuit board and is connected to the conductive pattern.
• The semiconductor device is located on the circuit board and is positioned next to the heat dissipating element.
• The semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

Abstract

A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

VARYING THE PO SPACE IN SEMICONDUCTOR LAYOUTS (17661795)

Main Inventor

Feng-Ming Chang

Brief explanation

The abstract describes a semiconductor device with multiple cells arranged in an array.

• Each cell consists of active regions arranged in one direction and conductive regions arranged in another direction.
• The conductive regions are spaced apart and positioned over the active regions.
• The first through fifth conductive regions contain one or more conductors.
• The conductors in the first and fifth regions have a larger dimension along the first direction compared to the conductors in the third region.
• The pitch (spacing) between conductors in the second and fourth regions is different from the pitch between a conductor in the second or fourth region and a conductor in the closest neighboring region that is not the second or fourth region.

Abstract

A semiconductor device comprising a plurality of cells arranged in an array is disclosed. Each cell comprises: at least one active region arranged along a first direction; and at least five spaced apart conductive regions arranged along a second direction disposed over the active regions, wherein the first through fifth conductive regions comprise one or more conductors, wherein the one or more conductors have a dimension along the first direction. The dimension along the first direction is larger for at least one conductor in the first or fifth conductive regions than the dimension along the first direction for a conductor in the third conductive region. The pitch between conductors in the second and the fourth conductive region and the pitch between a conductor in the second or fourth conductive region and a conductor in a next closest conductive region that is not the second or fourth conductive region are different.

METHOD AND STRUCTURE FOR REDUCE OTP CELL AREA AND LEAKAGE (18353351)

Main Inventor

Meng-Sheng Chang

Brief explanation

The patent application describes a memory device that includes multiple memory cells and a cross-arrangement of CPODE (Charge Pump Output Driver Enable) structures.

• The memory device consists of a first memory cell and a second memory cell.
• The first memory cell has a first polysilicon line associated with a first read word line and intersects a first active region and a second active region.
• The second memory cell has a third polysilicon line associated with a second read word line and intersects the same first and second active regions as the first memory cell.
• Both memory cells have a second polysilicon line and a CPODE structure associated with a program word line.
• The second polysilicon line intersects the first active region in the first memory cell and the second active region in the second memory cell.
• The CPODE structure intersects the second active region in the first memory cell and the first active region in the second memory cell.
• This arrangement forms a cross-arrangement of CPODE structures, which allows for efficient programming and reading of data in the memory device.

Abstract

A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORY (18353308)

Main Inventor

Yong-Sheng Huang

Brief explanation

The patent application describes a method for opening a source line in a memory device. 

• An erase gate line (EGL) and the source line are formed parallel to each other.
• The source line is separated from the EGL by a dielectric layer.
• A first etch is performed to create an opening through the EGL, stopping on the dielectric layer.
• A second etch is performed to thin the dielectric layer at the opening, using the same mask as the first etch.
• A silicide process is performed to form a silicide layer on the source line at the opening.
• The silicide process includes a third etch with a different mask, extending the opening through the dielectric layer.
• A via is formed through the EGL to connect to the silicide layer.

Abstract

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY (18354881)

Main Inventor

Wen-Tuo Huang

Brief explanation

The present application describes an integrated memory chip with a strap-cell architecture that reduces the number of distinct strap-cell types and strap-line density.

• The memory chip has a memory array with a strap-cell architecture that simplifies design and reduces complexity.
• The memory array is limited to three distinct types of strap cells: SLEG strap cell, CGWL strap cell, and word-line strap cell.
• The small number of distinct strap-cell types simplifies the design of the memory array and the corresponding interconnect structure.
• The strap cells electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers.
• By spreading the strap lines among different metallization layers, the density of strap lines is reduced.

Abstract

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

MEMORY DEVICE AND METHOD FOR FORMING THE SAME (17739871)

Main Inventor

Kuan-Ting CHEN

Brief explanation

The patent application describes a method for fabricating a semiconductor device with a ferroelectric gate structure. The method involves several steps, including depositing layers of ferroelectric and dielectric materials, patterning them to form a gate structure, and forming source/drain regions.

• Method for fabricating a semiconductor device with a ferroelectric gate structure
• Formation of a semiconductor layer over a substrate
• Deposition of a first ferroelectric layer over a channel region of the semiconductor layer
• Deposition of a first dielectric layer over the first ferroelectric layer
• Deposition of a second ferroelectric layer over the first dielectric layer
• Deposition of a gate metal layer over the second ferroelectric layer
• Patterning of the gate metal layer, second ferroelectric layer, first dielectric layer, and first ferroelectric layer to form a gate structure
• Formation of source/drain regions in the semiconductor layer on opposite sides of the gate structure

Abstract

A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

3D FERROELECTRIC MEMORY (18353954)

Main Inventor

Sheng-Chih Lai

Brief explanation

The patent application is for a metal-ferroelectric-insulator-semiconductor (MFIS) memory device and a method for forming it. 

• The MFIS memory device has a vertically stacked lower source/drain region and upper source/drain region.
• A semiconductor channel is located between the lower and upper source/drain regions.
• The control gate electrode extends along the sidewall of the semiconductor channel and the sidewalls of the lower and upper source/drain regions.
• A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

Abstract

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18354667)

Main Inventor

Meng-Han Lin

Brief explanation

The patent application describes a memory device with several components, including a word line, a source line, a bit line, a memory layer, and a channel material layer.

• The word line extends in one direction and has liner layers on its sidewall.
• The memory layer is located between the liner layers on the sidewall of the word line and extends along the sidewalls in the same direction.
• The liner layers are spaced apart by the memory layer and are sandwiched between the memory layer and the word line.
• The channel material layer is on the sidewall of the memory layer.
• A dielectric layer is on the sidewall of the channel material layer.
• The source line and the bit line are on opposite sides of the dielectric layer and are located on the sidewall of the channel material layer.
• The source line and the bit line extend in a direction perpendicular to the first direction.
• The material of the liner layers has a lower dielectric constant compared to the material of the memory layer.

Abstract

A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

METHOD OF FORMING FERROELECTRIC MEMORY DEVICE (17740331)

Main Inventor

Rainer Yen-Chieh Huang

Brief explanation

The patent application describes a method of forming a ferroelectric memory device.

• The method involves using atomic layer deposition (ALD) to form a ferroelectric layer between a gate electrode and a channel layer.
• The ALD process includes two sections: a first section where a first precursor is provided, and a second section where a first mixed precursor is provided.
• The first mixed precursor consists of a hafnium-containing precursor and a zirconium-containing precursor.
• The ferroelectric layer is directly formed as HfZrO with an orthorhombic phase (O-phase), which enhances the ferroelectric polarization and property of the device.

Abstract

Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as HfZrO with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF (18353972)

Main Inventor

Yu-Wei Jiang

Brief explanation

The abstract describes a semiconductor structure and a method for fabricating it. 

• The semiconductor structure includes a substrate and a stacked structure on the substrate.
• The stacked structure consists of insulating layers and gate members stacked alternately.
• A core structure is present within the stacked structure.
• The core structure comprises a memory layer, a channel member, a contact member, and a liner member.
• The channel member is located on top of the memory layer.
• The contact member is positioned on top of the channel member.
• The liner member surrounds a portion of the core structure.

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME (18354768)

Main Inventor

Tzu-Yu CHEN

Brief explanation

- The patent application describes a semiconductor device that includes a semiconductor substrate, a memory gate, and a data storage element.

- The semiconductor substrate has a memory well with two source/drain regions and a channel region between them. - The memory gate is positioned above the channel region. - The data storage element is made of a ferroelectric material and is placed around the memory gate to separate it from the channel region.

• The semiconductor device includes a memory gate and a data storage element.
• The memory gate is located above the channel region of the semiconductor substrate.
• The data storage element is made of a ferroelectric material.
• The data storage element surrounds the memory gate, providing separation from the channel region.
• The semiconductor substrate has a memory well with two source/drain regions.
• The memory gate and data storage element combination improves the performance and functionality of the semiconductor device.

Abstract

A semiconductor device includes a semiconductor substrate, a memory gate, and a data storage element. The semiconductor substrate includes a memory well which has two source/drain regions and a channel region between the source/drain regions. The memory gate is disposed above the channel region. The data storage element includes a ferroelectric material, and is disposed around the memory gate to separate the memory gate from the channel region.

BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY (18353988)

Main Inventor

Tzu-Yu Lin

Brief explanation

The patent application is for a new type of memory cell called a ferroelectric random-access memory (FeRAM) cell. 

• The FeRAM cell includes a bottom electrode, a switching layer, and a top electrode.
• The bottom-electrode interface structure is a dielectric material that separates the bottom electrode and the switching layer.
• The interface structure is designed to prevent metal atoms and impurities from the bottom electrode from diffusing into the switching layer.
• This prevents leakage current and increases the endurance of the memory cell.

Abstract

. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

MEMORY CELL WITH UNIPOLAR SELECTORS (18353290)

Main Inventor

Katherine H. Chiang

Brief explanation

The abstract describes an integrated chip that includes a magnetic tunnel junction (MTJ) and two unipolar selectors.

• The integrated chip has a MTJ, which is a type of device used in magnetic memory storage.
• The MTJ is located on a first electrode within a dielectric structure over a substrate.
• The chip also includes two unipolar selectors, which are devices used to control the flow of electrical current.
• The first unipolar selector is electrically connected to the first electrode.
• The second unipolar selector is also electrically connected to the first electrode.
• The first unipolar selector extends laterally between a vertical line intersecting the MTJ and the substrate.
• The second unipolar selector extends laterally between a vertical line intersecting the second unipolar selector and the substrate.

Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a magnetic tunnel junction (MTJ) disposed on a first electrode within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. The first unipolar selector laterally extends between a first vertical line intersecting the MTJ and the substrate and a second vertical line intersecting the second unipolar selector and the substrate.

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES (18356585)

Main Inventor

Sheng-Chih Lai

Brief explanation

The patent application is about a bipolar selector with independently tunable threshold voltages and a memory cell and memory array comprising the selector.

• The bipolar selector consists of two unipolar selectors, which are diodes or similar devices.
• The first and second unipolar selectors are connected in parallel with opposite orientations.
• This arrangement allows the first unipolar selector to define one threshold voltage and the second unipolar selector to define another threshold voltage independently.
• The threshold voltages can be adjusted by modifying the parameters of the unipolar selectors.
• This innovation provides flexibility in tuning the threshold voltages of the bipolar selector, enhancing its performance in memory cells and arrays.

Abstract

Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

METHOD FOR FORMING A HARD MASK WITH A TAPERED PROFILE (18353254)

Main Inventor

Min-Yung Ko

Brief explanation

- The patent application describes a method for forming a memory cell.

- A memory film is deposited over a substrate, consisting of a bottom electrode layer, a top electrode layer, and a data storage film between them. - A hard mask film is then deposited over the memory film, which includes a conductive hard mask layer. - The top electrode layer and the hard mask film are patterned to create a top electrode and a hard mask over it. - A trimming process is performed to reduce the angle between the sidewall of the hard mask and the bottom surface of the hard mask. - An etch is then carried out into the data storage film using the hard mask as a guide, resulting in the formation of a data storage structure beneath the top electrode.

Abstract

Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

MEMORY DEVICE (18355385)

Main Inventor

Yen-Lin Huang

Brief explanation

The patent application describes a memory device that includes a substrate, a spin-orbit torque layer, and a magnetic tunneling junction (MTJ).

• The memory device is designed to store and retrieve data.
• The MTJ is stacked with the spin-orbit torque layer over the substrate.
• The MTJ includes a synthetic free layer, a barrier layer, and a reference layer.
• The synthetic free layer consists of a synthetic antiferromagnetic structure, a first spacer layer, and a free layer.
• The synthetic antiferromagnetic structure is located between the spin-orbit torque layer and the free layer.
• The barrier layer is positioned beside the synthetic free layer.
• The reference layer is positioned beside the barrier layer.

Abstract

A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME (18356168)

Main Inventor

Georgios Vellianitis

Brief explanation

The patent application describes a semiconductor structure with a storage element layer and a selector.

• The selector is connected to the storage element layer and consists of multiple insulating layers and conductive layers.
• The insulating layers are stacked in a specific sequence, with the second insulating layer sandwiched between the first and third insulating layers.
• The first and third insulating layers have materials with a higher band gap compared to the material of the second insulating layer.
• The first conductive layer is connected to the first insulating layer, and the second conductive layer is connected to the third insulating layer.

Abstract

A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

MEMORY STACKS AND METHODS OF FORMING THE SAME (18356180)

Main Inventor

Tung-Ying Lee

Brief explanation

The abstract describes a memory stack and a method of forming it.

• The memory stack consists of a bottom electrode layer, a top electrode layer, and a phase change layer.
• The top electrode layer is wider than the phase change layer.
• A portion of the top electrode layer that is not covered by the phase change layer is rougher than the portion covered by it.

Abstract

Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.