US Patent Application 18353351. METHOD AND STRUCTURE FOR REDUCE OTP CELL AREA AND LEAKAGE simplified abstract

METHOD AND STRUCTURE FOR REDUCE OTP CELL AREA AND LEAKAGE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Meng-Sheng Chang of Hsinchu (TW)

Chia-En Huang of Hsinchu (TW)

Shao-Yu Chou of Hsinchu (TW)

Yih Wang of Hsinchu (TW)

METHOD AND STRUCTURE FOR REDUCE OTP CELL AREA AND LEAKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18353351 titled 'METHOD AND STRUCTURE FOR REDUCE OTP CELL AREA AND LEAKAGE

Simplified Explanation

The patent application describes a memory device that includes multiple memory cells and a cross-arrangement of CPODE (Charge Pump Output Driver Enable) structures.

• The memory device consists of a first memory cell and a second memory cell.
• The first memory cell has a first polysilicon line associated with a first read word line and intersects a first active region and a second active region.
• The second memory cell has a third polysilicon line associated with a second read word line and intersects the same first and second active regions as the first memory cell.
• Both memory cells have a second polysilicon line and a CPODE structure associated with a program word line.
• The second polysilicon line intersects the first active region in the first memory cell and the second active region in the second memory cell.
• The CPODE structure intersects the second active region in the first memory cell and the first active region in the second memory cell.
• This arrangement forms a cross-arrangement of CPODE structures, which allows for efficient programming and reading of data in the memory device.

Original Abstract Submitted

A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.