US Patent Application 18353308. ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORY simplified abstract

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ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORY

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Yong-Sheng Huang of Taipei (TW)

Ming Chyi Liu of Hsinchu City (TW)

Chih-Pin Huang of Hsinchu City (TW)

ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18353308 titled 'ETCH METHOD FOR OPENING A SOURCE LINE IN FLASH MEMORY

Simplified Explanation

The patent application describes a method for opening a source line in a memory device.

  • An erase gate line (EGL) and the source line are formed parallel to each other.
  • The source line is separated from the EGL by a dielectric layer.
  • A first etch is performed to create an opening through the EGL, stopping on the dielectric layer.
  • A second etch is performed to thin the dielectric layer at the opening, using the same mask as the first etch.
  • A silicide process is performed to form a silicide layer on the source line at the opening.
  • The silicide process includes a third etch with a different mask, extending the opening through the dielectric layer.
  • A via is formed through the EGL to connect to the silicide layer.


Original Abstract Submitted

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

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