US Patent Application 18352270. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Min-Feng Kao of Chiayi City (TW)

Dun-Nian Yaung of Taipei City (TW)

Jen-Cheng Liu of Hsin-Chu City (TW)

Hsing-Chih Lin of Tainan City (TW)

Zheng-Xun Li of Tainan City (TW)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18352270 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a semiconductor structure and a method for manufacturing it.

  • The semiconductor structure consists of three tiers: top, middle, and bottom.
  • The bottom tier includes a first interconnect structure and a first front-side bonding structure.
  • The middle tier is placed between the top and bottom tiers and is electrically connected to them.
  • The middle tier includes a second interconnect structure, a second front-side bonding structure, and a back-side bonding structure.
  • The second front-side bonding structure has a bonding feature that includes a first bonding via, a first bonding contact, and a barrier layer interface.
  • The first bonding via is in contact with the second interconnect structure.
  • The first bonding contact overlies the first bonding via.
  • The barrier layer interface is between the bottom of the first bonding contact and the top of the first bonding via.
  • The manufacturing method for the semiconductor structure is not described in detail in the abstract.


Original Abstract Submitted

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.

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