US Patent Application 18354881. STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY simplified abstract

STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Wen-Tuo Huang of Tainan City (TW)

Ping-Cheng Li of Kaohsiung City (TW)

Hung-Ling Shih of Tainan City (TW)

Po-Wei Liu of Tainan City (TW)

Yu-Ling Hsu of Tainan City (TW)

Yong-Shiuan Tsair of Tainan City (TW)

Chia-Sheng Lin of Tainan City (TW)

Shih Kuang Yang of Tainan City (TW)

STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18354881 titled 'STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY

Simplified Explanation

The present application describes an integrated memory chip with a strap-cell architecture that reduces the number of distinct strap-cell types and strap-line density.

• The memory chip has a memory array with a strap-cell architecture that simplifies design and reduces complexity.
• The memory array is limited to three distinct types of strap cells: SLEG strap cell, CGWL strap cell, and word-line strap cell.
• The small number of distinct strap-cell types simplifies the design of the memory array and the corresponding interconnect structure.
• The strap cells electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers.
• By spreading the strap lines among different metallization layers, the density of strap lines is reduced.

Original Abstract Submitted

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.