US Patent Application 17661858. SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING simplified abstract

SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Hsien-Wei Chen of Hsinchu City (TW)

Meng-Liang Lin of Hsinchu (TW)

Shin-Puu Jeng of Hsinchu (TW)

SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING - A simplified explanation of the abstract

This abstract first appeared for US patent application 17661858 titled 'SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING

Simplified Explanation

The patent application describes a semiconductor package for high-performance computing.

• The package includes an integrated circuit die connected to an interposer.
• The interposer has connection structures on its bottom surface.
• The top surface of the interposer has test contact structures connected to the integrated circuit die.
• These test contact structures can be probed to test the quality and reliability of the integrated circuit die and the functionality of the interposer traces.
• By testing the integrated circuit die and interposer traces through the test contact structures, the connection structures are not probed, reducing the risk of damage to the solder joints between the connection structures and the substrate.
• This improves the reliability and quality of the semiconductor package.

Original Abstract Submitted

A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures. In this way, damage to the connection structures, due to probing, may be avoided to improve a reliability and/or a quality of solder joints between the connection structures and a substrate to which the interposer is subsequently mounted.