US Patent Application 18353954. 3D FERROELECTRIC MEMORY simplified abstract

3D FERROELECTRIC MEMORY

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Sheng-Chih Lai of Hsinchu County (TW)

Chung-Te Lin of Tainan City (TW)

3D FERROELECTRIC MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18353954 titled '3D FERROELECTRIC MEMORY

Simplified Explanation

The patent application is for a metal-ferroelectric-insulator-semiconductor (MFIS) memory device and a method for forming it.

• The MFIS memory device has a vertically stacked lower source/drain region and upper source/drain region.
• A semiconductor channel is located between the lower and upper source/drain regions.
• The control gate electrode extends along the sidewall of the semiconductor channel and the sidewalls of the lower and upper source/drain regions.
• A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

Original Abstract Submitted

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.