US Patent Application 17737998. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Wei-Ming Wang of Taichung City (TW)

Yu-Hung Lin of Taichung City (TW)

Shih-Peng Tai of Hsinchu County (TW)

Kuo-Chung Yee of Taoyuan City (TW)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17737998 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package with multiple dies and an interlink structure.

  • The package includes a substrate, a first die, and a second die.
  • The first die is thicker than the second die.
  • A resistant layer is placed on both dies, covering them completely.
  • An encapsulant is applied on top of the resistant layer, surrounding the first and second dies.
  • The interlink structure is positioned above the dies and embedded in the encapsulant.
  • The interlink structure is electrically connected to both the first and second dies.
  • The interlink structure consists of a first via portion connected to the first die, a second via portion connected to the second die, and a routing line portion connecting the two via portions.
  • The first via portion is shorter than the second via portion.


Original Abstract Submitted

A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.

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