US Patent Application 18224065. SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Shin-Yi Yang of New Taipei (TW)
SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18224065 titled 'SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
Simplified Explanation
- The patent application describes an integrated circuit die with edge interconnect features. - These edge interconnect features are conductive lines that extend through sealing rings and are exposed on the edge surfaces of the integrated circuit die. - The purpose of these edge interconnect features is to connect with other integrated circuit dies without the need for an interposer. - The semiconductor device can include multiple integrated circuit dies with edge interconnect features, which are connected through inter-chip connectors formed between them. - The inter-chip connectors can be formed using a selective bumping process during packaging.
Original Abstract Submitted
Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.
