US Patent Application 18353988. BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY simplified abstract
Contents
BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Tzu-Yu Lin of Taoyuan City (TW)
Chia-Wen Zhong of Taichung City (TW)
BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18353988 titled 'BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY
Simplified Explanation
The patent application is for a new type of memory cell called a ferroelectric random-access memory (FeRAM) cell.
- The FeRAM cell includes a bottom electrode, a switching layer, and a top electrode.
- The bottom-electrode interface structure is a dielectric material that separates the bottom electrode and the switching layer.
- The interface structure is designed to prevent metal atoms and impurities from the bottom electrode from diffusing into the switching layer.
- This prevents leakage current and increases the endurance of the memory cell.
Original Abstract Submitted
. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.
