US Patent Application 18052204. CALIBRATION SYSTEM OF CANCELING EFFECT OF PHASE NOISE AND ANALOG-TO-DIGITAL CONVERTING DEVICE COMPRISING THE SAME simplified abstract

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CALIBRATION SYSTEM OF CANCELING EFFECT OF PHASE NOISE AND ANALOG-TO-DIGITAL CONVERTING DEVICE COMPRISING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Ting-Hao Wang of HSINCHU CITY (TW)

Jieh-Tsorng Wu of HSINCHU CITY (TW)

CALIBRATION SYSTEM OF CANCELING EFFECT OF PHASE NOISE AND ANALOG-TO-DIGITAL CONVERTING DEVICE COMPRISING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18052204 titled 'CALIBRATION SYSTEM OF CANCELING EFFECT OF PHASE NOISE AND ANALOG-TO-DIGITAL CONVERTING DEVICE COMPRISING THE SAME

Simplified Explanation

The patent application describes a calibration system that includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit, and a first calculation circuit.

  • The jitter-capturing ADC samples a clock signal using an operating clock signal to generate a first quantized output.
  • The calibration value generating circuit receives the first quantized output and a second quantized output from a to-be-calibrated ADC to generate a calibration value.
  • The operating clock signal drives the to-be-calibrated ADC for sampling, and the calibration value is related to the phase noise of the operating clock signal.
  • The first calculation circuit subtracts the calibration value from the second quantized output to generate a third quantized output.


Original Abstract Submitted

A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

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