US Patent Application 18353997. VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE simplified abstract

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VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Te-Hsien Hsieh of Kaohsiung City (TW)

Yu-Hsing Chang of Taipei City (TW)

Yi-Min Chen of Hsinchu City (TW)

VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18353997 titled 'VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE

Simplified Explanation

The patent application describes an integrated chip with a conductive structure embedded in a substrate or a dielectric layer.

  • The conductive structure is surrounded by a first barrier layer on its sides and bottom, and a second barrier layer on top of the first barrier layer.
  • The second barrier layer separates the first barrier layer from the substrate or dielectric layer.
  • A second dielectric layer is placed on top of the substrate or dielectric layer.
  • A via structure extends through the second dielectric layer and is directly connected to the conductive structure through the first and second barrier layers.


Original Abstract Submitted

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

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