US Patent Application 18352271. SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER simplified abstract
SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Ching-Jung Yang of Taoyuan City (TW)
Hsien-Wei Chen of Hsinchu City (TW)
Jie Chen of New Taipei City (TW)
Ming-Fa Chen of Taichung City (TW)
SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18352271 titled 'SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER
Simplified Explanation
The patent application describes a semiconductor structure that includes two semiconductor dies stacked on top of each other, with a passivation layer covering the top die.
- The structure includes a first semiconductor die and a second semiconductor die stacked on top of each other.
- A passivation layer is applied over the second semiconductor die, covering it completely.
- The passivation layer has openings that reveal the pads of the second semiconductor die.
- An anti-arcing pattern is placed on top of the passivation layer.
- Conductive terminals are placed on top of the anti-arcing pattern and are electrically connected to the pads of the second semiconductor die.
Original Abstract Submitted
A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
