Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on December 14th, 2023

Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on December 14th, 2023

CHARGED PARTICLE FILTER AND REMOVAL SYSTEM (17839343)

Main Inventor

En Tian LIN

Brief explanation

The patent application describes a filter that uses two conductive meshes to remove contaminants from a fluid. The first conductive mesh is positively charged, while the second conductive mesh is negatively charged. Anions in the fluid or generated by an electrical field between the meshes interact with the contaminants, attracting them to the meshes.

• The filter uses two oppositely charged conductive meshes to remove contaminants from a fluid.
• The first mesh is positively charged, and the second mesh is negatively charged.
• Anions in the fluid or generated by an electrical field between the meshes interact with the contaminants, attracting them to the meshes.

Potential Applications

• Water purification systems
• Air filtration systems
• Industrial filtration processes

Problems Solved

• Efficient removal of contaminants from fluids
• Enhanced filtration performance
• Reduction of contaminants in water or air

Benefits

• Improved filtration efficiency
• Lower maintenance requirements
• Enhanced purification of fluids

Abstract

The present disclosure is directed to at least one embodiment of a filter that is configured to remove contaminants utilizing a first conductive mesh (e.g., first electrode) and a second conductive mesh (e.g., second electrode) that extends around the first conductive mesh. For example, the first conductive mesh may receive a first electrical signal and the second conductive mesh may receive a second electrical signal such that the first and second conductive meshes are oppositely charged from each other (e.g., the first conductive mesh is positively charged and the second conductive mesh is negatively charged). Anions that are present within the fluid or generated by an electrical field between the first and second conductive meshes may interact with the contaminants such that the contaminants are attracted to at least one of the first and second conductive meshes, respectively.

Polishing Pad for Chemical Mechanical Polishing and Method (17822867)

Main Inventor

Te-Chien Hou

Brief explanation

The abstract describes a patent application for polishing pads with varying protrusions and methods of making them. The polishing pad includes a substrate, a first protrusion with a central region and a peripheral region, and a first groove adjacent to the first side of the first protrusion.

• The patent application is for polishing pads with varying protrusions.
• The polishing pad includes a substrate, which serves as the base for the pad.
• The pad has a first protrusion with a central region and a peripheral region.
• The central region of the protrusion has a higher hardness than the peripheral region.
• The pad also has a first groove adjacent to one side of the first protrusion.

Potential applications of this technology:

• Polishing and finishing surfaces in various industries such as automotive, electronics, and optics.
• Removing scratches, imperfections, or blemishes from surfaces.
• Achieving a smooth and polished finish on different materials like metal, glass, or plastic.

Problems solved by this technology:

• Uneven polishing or finishing of surfaces due to the uniform hardness of traditional polishing pads.
• Inefficient removal of scratches or imperfections on surfaces.
• Lack of control over the polishing process, resulting in inconsistent results.

Benefits of this technology:

• Improved polishing efficiency and effectiveness.
• Enhanced control over the polishing process for achieving desired results.
• Reduced time and effort required for surface polishing.
• Consistent and uniform finish on various materials.

Abstract

Polishing pads having varying protrusions and methods of forming the same are disclosed. In an embodiment, a polishing pad includes a polishing pad substrate; a first protrusion on the polishing pad substrate, the first protrusion including a central region and a peripheral region surrounding the central region, and a first hardness of the central region being greater than a second hardness of the peripheral region; and a first groove adjacent a first side of the first protrusion.

MICRO-ELECTROMECHANICAL SYSTEMS (MEMS) DEVICE WITH OUTGAS LAYER (17835175)

Main Inventor

Fan Hu

Brief explanation

The present disclosure describes an integrated chip that includes a semiconductor device substrate and multiple semiconductor devices arranged on it. The chip also includes a micro-electromechanical system (MEMS) layer, which has two moveable masses. A capping layer covers the MEMS layer, with one surface directly over each moveable mass. An outgas layer is present on the surface over the first moveable mass, creating a cavity for it, while the surface over the second moveable mass creates a separate cavity for it.

• Integrated chip with semiconductor devices and a MEMS layer
• MEMS layer includes two moveable masses
• Capping layer covers the MEMS layer
• Outgas layer creates a cavity for the first moveable mass
• Separate cavity is created for the second moveable mass

Potential applications of this technology:

• Micro-electromechanical systems (MEMS) devices
• Sensors and actuators
• Microfluidics and lab-on-a-chip systems

Problems solved by this technology:

• Integration of semiconductor devices and MEMS devices on a single chip
• Providing separate cavities for multiple moveable masses

Benefits of this technology:

• Compact design with integrated functionality
• Improved performance and reliability of MEMS devices
• Cost-effective manufacturing process

Abstract

The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.

SEMICONDUCTOR PROCESS CHAMBER WITH IMPROVED REFLECTOR (17837910)

Main Inventor

Sou-Chuan CHIANG

Brief explanation

The patent application describes a substrate processing chamber used for epitaxial deposition processes. The chamber includes a substrate support, a reflector, heating elements, support kits, and a cooling plate.

• The substrate support has an upper surface where the substrate is placed.
• The reflector is positioned above the substrate support and has a body with an upper opening and a bottom opening. The body also has a flange with holes.
• The heating elements are placed around the reflector and emit energy radiation.
• The support kits consist of a bar member and a fastener that can be attached to the holes in the flange. They help secure the reflector at a height that allows better distribution of energy radiation across the substrate support.
• The cooling plate is connected to the flange using the support kits and has an opening that allows the body of the reflector to pass through.

Potential applications of this technology:

• Epitaxial deposition processes in semiconductor manufacturing.
• Thin film deposition for electronic devices.
• Solar cell manufacturing.

Problems solved by this technology:

• Blockage of energy radiation caused by the reflector can be reduced, leading to more uniform heating of the substrate.
• The reflector can be securely positioned at an optimal height, improving the efficiency of the deposition process.

Benefits of this technology:

• Improved uniformity and efficiency in epitaxial deposition processes.
• Enhanced control over the heating and cooling of the substrate.
• Increased productivity and yield in semiconductor manufacturing.

Abstract

A substrate processing chamber for performing an epitaxial deposition process is provided. The chamber includes a substrate support having an upper surface, a reflector disposed above the substrate support. The reflector includes a body comprising an upper opening having a first diameter, a bottom opening having a second diameter less than the first diameter, and a flange protruding radially from an outer circumference of the body around the upper opening, wherein the flange comprises a plurality of holes. The chamber includes a plurality of heating elements disposed around the reflector, each heating element being operable to emit energy radiation, a plurality of support kits, each support kit comprising a bar member and a fastener removably coupled to the bar member, wherein the bar member and fastener are configured to secure to the respective hole in the flange so that the reflector is at a height that reduces blockage of the energy radiation and increases an amount of the energy radiation to be distributed across the upper surface of the substrate support. The chamber further includes a cooling plate coupled to the flange by the plurality of support kits, wherein the cooling plate comprises an opening sized to allow passage of the body of the reflector.

NOVEL JITTER NOISE DETECTOR (18232341)

Main Inventor

Tien-Chien HUANG

Brief explanation

The abstract describes a noise detection circuit that includes transistors and a latch circuit to detect timing differences between clock signals. Here is a simplified explanation of the abstract:

• The noise detection circuit consists of a first transistor that receives a delayed version of a clock signal and a second transistor that receives a delayed version of a reference clock signal.
• The circuit also includes a latch circuit that is connected to the first transistor at a first node and to the second transistor at a second node.
• The latch circuit is designed to latch the logic states of voltage levels at the first and second nodes based on whether the timing difference between the transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

Potential applications of this technology:

• Noise detection circuits can be used in various electronic devices and systems where accurate timing is crucial, such as communication systems, data storage devices, and digital signal processing.
• It can be used in high-speed data transmission systems to detect and mitigate noise or interference that can affect the integrity of the transmitted data.
• The circuit can also be used in clock synchronization systems to ensure precise timing between different components or subsystems.

Problems solved by this technology:

• The noise detection circuit addresses the problem of timing discrepancies between clock signals and reference signals, which can lead to errors or malfunctions in electronic systems.
• By detecting and latching the logic states of voltage levels based on timing differences, the circuit can identify and mitigate noise or interference that can disrupt the proper functioning of electronic devices.

Benefits of this technology:

• The circuit provides a reliable and efficient method for detecting and addressing timing discrepancies in electronic systems.
• It allows for accurate synchronization of clock signals, ensuring the proper operation of electronic devices.
• By detecting and mitigating noise or interference, the circuit helps improve the overall performance and reliability of electronic systems.

Abstract

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

PHOTONIC DEVICE, SYSTEM AND METHOD OF MAKING SAME (17836879)

Main Inventor

Weiwei SONG

Brief explanation

The patent application describes a method for making photonic devices and systems using a substrate, insulator layers, waveguide layers, and insulator spacers. The method involves forming waveguide patterns at different vertical levels and coupling at least two of these patterns.

• The method involves providing a substrate and forming an insulator layer over it.
• Multiple waveguide layers and insulator spacers are deposited at different vertical levels over the insulator layer.
• The waveguide layers are isolated by the insulator spacers.
• Waveguide patterns are formed at the different waveguide layers.
• At least two waveguide patterns at different vertical levels are coupled together.

Potential applications of this technology:

• Optical communication systems
• Optical computing
• Photonic integrated circuits
• Optical sensors
• Biomedical imaging

Problems solved by this technology:

• Enables the fabrication of complex photonic devices and systems with multiple waveguide layers.
• Provides a method for coupling waveguide patterns at different vertical levels, allowing for more efficient and compact designs.
• Offers a simplified and scalable approach for manufacturing photonic devices.

Benefits of this technology:

• Increased functionality and performance of photonic devices and systems.
• Improved integration and miniaturization of optical components.
• Enhanced efficiency and reliability of optical communication and computing systems.
• Potential for cost reduction in the manufacturing process.

Abstract

Photonic device, system and methods of making photonic devices and systems, the method including: providing a substrate, forming an insulator layer over the substrate, depositing a plurality of waveguide layers and a plurality of insulator spacers at different vertical levels over the insulator layer, wherein adjacent waveguide layers in the plurality of waveguide layers are isolated by one or more insulator spacers in the plurality of insulator spacers, and forming a plurality of waveguide patterns at the plurality of waveguide layers, wherein at least two waveguide patterns at different vertical levels in the plurality of waveguide patterns are coupled.

EDGE COUPLERS AND METHODS OF MAKING THE SAME (18232319)

Main Inventor

Min-Hsiang HSU

Brief explanation

The patent application describes edge couplers that have a high coupling efficiency and low polarization dependent loss. These edge couplers are used for optically coupling an optical waveguide to an optical fiber placed at the edge of a semiconductor device.

• The semiconductor device includes a substrate, an optical waveguide, and a plurality of layers.
• The plurality of layers includes a plurality of coupling pillars that are located at the edge of the semiconductor device.
• The coupling pillars form an edge coupler that is designed to efficiently couple the optical waveguide to the optical fiber.

Potential Applications

• Optical communication systems
• Fiber optic networks
• Integrated photonics devices

Problems Solved

• Low coupling efficiency between optical waveguides and optical fibers
• High polarization dependent loss in edge couplers

Benefits

• High coupling efficiency
• Low polarization dependent loss
• Improved performance of optical communication systems
• Better integration of photonics devices

Abstract

Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.

OPTICAL COUPLING APPARATUS AND METHODS OF MAKING SAME (18232342)

Main Inventor

Chan-Hong CHERN

Brief explanation

The patent application discloses an apparatus and methods for optical coupling in optical communications. The apparatus includes a planar layer with an array of scattering elements arranged in a two-dimensional grating. The scattering elements are pillars with concave polygon-shaped top surfaces.

• The apparatus includes a planar layer with an array of scattering elements arranged in a two-dimensional grating.
• The scattering elements are pillars with concave polygon-shaped top surfaces.
• The grating is formed by intersecting concentric elliptical curves.
• A first taper structure connects one side of the grating to a first waveguide.
• A second taper structure connects the other side of the grating to a second waveguide.

Potential applications of this technology:

• Optical communications systems
• Fiber optic networks
• Data centers
• Telecommunications infrastructure

Problems solved by this technology:

• Efficient optical coupling between waveguides and scattering elements
• Improved light transmission and reception in optical communications systems
• Enhanced performance and reliability of fiber optic networks

Benefits of this technology:

• Improved optical coupling efficiency
• Increased data transmission rates
• Enhanced signal quality and reliability
• Reduced signal loss and distortion

Abstract

Disclosed are apparatus and methods for optical coupling in optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a planar layer; an array of scattering elements arranged in the planar layer at a plurality of intersections of a first set of concentric elliptical curves crossing with a second set of concentric elliptical curves rotated proximately 90 degrees to form a two-dimensional (2D) grating; a first taper structure formed in the planar layer connecting a first convex side of the 2D grating to a first waveguide; and a second taper structure formed in the planar layer connecting a second convex side of the 2D grating to a second waveguide. Each scattering element is a pillar into the planar layer. The pillar has a top surface whose shape is a concave polygon having at least 6 corners.

MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS (18231760)

Main Inventor

Hsin-Yu CHEN

Brief explanation

The abstract describes a method for creating a cost-effective collimator structure for contact image sensors that filters out ambient infrared light to reduce noise. The structure includes a dielectric layer, a substrate, a series of via holes, and a conductive layer. The via holes are arranged in an array along the surface of the dielectric layer and extend through both the dielectric layer and the substrate. The conductive layer is applied to the surface of the dielectric layer and the sidewalls of the via holes, allowing the collimator to filter light within a specific range of wavelengths.

• The method provides a cost-effective way to fabricate a collimator structure for contact image sensors.
• The structure filters out ambient infrared light to reduce noise.
• The structure includes a dielectric layer, a substrate, via holes, and a conductive layer.
• The via holes are arranged in an array along the surface of the dielectric layer and extend through both the dielectric layer and the substrate.
• The conductive layer is applied to the surface of the dielectric layer and the sidewalls of the via holes.
• The conductive layer allows the collimator to filter light within a specific range of wavelengths.

Potential Applications

This technology can be applied in various fields where contact image sensors are used, such as:

• Document scanning
• Barcode scanning
• Biometric authentication
• Optical character recognition (OCR)
• Image processing

Problems Solved

This technology addresses the following problems:

• Ambient infrared light causing noise in contact image sensors
• Expensive fabrication methods for collimator structures
• Inefficient filtering of light in contact image sensors

Benefits

The benefits of this technology include:

• Cost-effective fabrication method for collimator structures
• Reduction of noise caused by ambient infrared light
• Improved filtering of light in contact image sensors
• Enhanced performance and accuracy in applications using contact image sensors

Abstract

Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.

LITHOGRAPHY SYSTEM AND METHODS (18446400)

Main Inventor

Cheng Hung TSAI

Brief explanation

The patent application describes a method for lithography, a process used in semiconductor manufacturing. The method involves depositing a mask layer on a substrate and directing radiation from a sectional collector of a lithography system onto the mask layer to create a pattern. The radiation is directed from both a central collector section and a peripheral collector section, which are separated by a gap. The method further includes forming openings in the mask layer by removing regions exposed to the radiation and removing material from the underlying layer exposed by the openings.

• The method involves depositing a mask layer on a substrate.
• Radiation from a sectional collector is directed onto the mask layer to create a pattern.
• The radiation is directed from both a central collector section and a peripheral collector section.
• The central and peripheral collector sections are separated by a gap.
• Openings are formed in the mask layer by removing regions exposed to the radiation.
• Material from the underlying layer exposed by the openings is removed.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuit fabrication
• Nanotechnology research

Problems solved by this technology:

• Provides a method for creating precise patterns on a mask layer for semiconductor manufacturing.
• Allows for the removal of material from an underlying layer with accuracy and control.

Benefits of this technology:

• Enables the production of high-quality integrated circuits with precise patterns.
• Improves the efficiency and accuracy of lithography processes.
• Facilitates advancements in semiconductor manufacturing and nanotechnology research.

Abstract

A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.

METHOD OF USING WAFER STAGE (18448110)

Main Inventor

Yung-Yao LEE

Brief explanation

The patent application describes a method of controlling a wafer stage in semiconductor manufacturing. The method involves moving an immersion hood over different sensors and areas on the wafer stage to perform various tasks.

• The wafer stage is moved to position an immersion hood over a first sensor.
• The wafer stage is then moved to position the immersion hood over a second sensor.
• After that, the wafer stage is moved to position the immersion hood over a first particle capture area on the wafer stage.
• The wafer stage is further moved to define a routing track over the first particle capture area.
• Finally, the wafer stage is moved to position the immersion hood over an area for receiving a wafer on the wafer stage.

Potential applications of this technology:

• Semiconductor manufacturing: This method can be used in the production of semiconductor wafers to control the movement of the wafer stage and perform various tasks accurately and efficiently.

Problems solved by this technology:

• Precise positioning: The method allows for precise positioning of the immersion hood over different sensors and areas on the wafer stage, ensuring accurate measurements and operations.

Benefits of this technology:

• Improved efficiency: By automating the movement of the wafer stage and immersion hood, the method can increase the efficiency of semiconductor manufacturing processes.
• Enhanced accuracy: The precise positioning of the immersion hood over sensors and areas on the wafer stage improves the accuracy of measurements and operations.
• Particle capture: The method includes a particle capture area on the wafer stage, which helps in capturing and removing particles that may affect the quality of the wafer.

Abstract

A method of controlling a wafer stage includes moving the wafer stage to position an immersion hood over a first sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a second sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor. The method further includes moving the wafer stage to define a routing track over the first particle capture area. The method further includes moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.

LITHOGRAPHY SYSTEM AND METHOD THEREOF (18361728)

Main Inventor

Shao-Hua WANG

Brief explanation

The patent application describes a lithography system that includes various components such as a table body, a wafer stage, sliding members, cables, brackets, rail guides, and protective films. The system allows for precise movement and positioning of the wafer stage during the lithography process.

• The first sliding member is connected to the wafer stage, allowing it to move along a track on the second sliding member, which is attached to the table body.
• A first cable is fixed by a bracket, which is part of a roller structure. The roller structure consists of a body and a wheel.
• The wheel of the roller structure moves along a rail guide, which restricts its movement.
• A first protective film is applied to the surface of the rail guide, providing a smooth surface for the roller structure to move along.

Potential applications of this technology:

• Lithography systems used in semiconductor manufacturing processes.
• Precision positioning and movement of the wafer stage during lithography.
• Ensuring smooth and controlled movement of components in a lithography system.

Problems solved by this technology:

• Provides a stable and controlled movement of the wafer stage during lithography, ensuring accurate positioning.
• Reduces friction and wear on the components involved in the movement.
• Protects the rail guide surface from damage or contamination.

Benefits of this technology:

• Improved accuracy and precision in lithography processes.
• Increased lifespan and reliability of the components involved in the movement.
• Reduced maintenance and downtime due to wear or damage.

Abstract

A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.

MITIGATING LONG-TERM ENERGY DECAY OF LASER DEVICES (18210548)

Main Inventor

Chih-Ping YEN

Brief explanation

The patent application describes an apparatus for manufacturing semiconductors that includes a power amplifier, a catalyst, an inlet port, and an exhaust port. During a cleaning operation, a mixing gas is introduced through the inlet port into the power amplifier, where it contacts a catalyst surface with a build-up. The mixing gas reacts with the build-up, generating gaseous by-products that are then removed through the exhaust port.

• The apparatus is used for manufacturing semiconductors.
• It includes a power amplifier to power a laser.
• A catalyst is placed in the power amplifier.
• An inlet port introduces a mixing gas into the power amplifier during a cleaning operation.
• The mixing gas contacts the catalyst surface with a build-up.
• The mixing gas reacts with the build-up, generating gaseous by-products.
• An exhaust port removes the gaseous by-products from the power amplifier.

Potential Applications

This technology can be applied in various semiconductor manufacturing processes, including but not limited to:

• Fabrication of integrated circuits
• Production of solar cells
• Manufacturing of microprocessors

Problems Solved

The apparatus addresses the following problems encountered in semiconductor manufacturing:

• Build-up on the catalyst surface can negatively impact the performance and efficiency of the power amplifier.
• Manual cleaning methods are time-consuming and may not effectively remove the build-up.
• The presence of build-up can lead to defects in the manufactured semiconductors.

Benefits

The use of this apparatus offers several benefits in semiconductor manufacturing:

• Improved performance and efficiency of the power amplifier by removing build-up on the catalyst surface.
• Enhanced reliability and quality of the manufactured semiconductors.
• Time and cost savings compared to manual cleaning methods.
• Increased productivity and throughput in the manufacturing process.

Abstract

An apparatus for manufacturing semiconductors includes a power amplifier to power a laser, a catalyst disposed in the power amplifier, an inlet port, and an exhaust port. The inlet port introduces a mixing gas to an interior of the power amplifier during a cleaning operation so that the mixing gas contacts a surface of the catalyst having a build-up thereon. The mixing gas reacts with and removes the build-up by generating gaseous by-products. The exhaust port removes the gaseous by-products from the power amplifier.

INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME (17825383)

Main Inventor

Ching-Yu HUANG

Brief explanation

The patent application describes a method for designing and manufacturing integrated circuits. Here are the key points:

• The method involves identifying contact vias in a standard cell, which connect active regions and conductive lines.
• The cell height is calculated based on the width of the active regions.
• Multiple available cell heights are calculated based on the ratio between the widths of the active regions.
• Layout designs of multiple cells are generated based on the calculated cell heights.
• The integrated circuit is manufactured based on the layout designs.

Potential applications of this technology:

• Integrated circuit design and manufacturing
• Semiconductor industry

Problems solved by this technology:

• Efficient design of integrated circuits
• Optimal utilization of available space in the circuit layout

Benefits of this technology:

• Improved performance and functionality of integrated circuits
• Cost-effective design and manufacturing process
• Increased productivity in the semiconductor industry

Abstract

A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

SYSTEMS AND METHODS FOR CONTEXT AWARE CIRCUIT DESIGN (18232742)

Main Inventor

Li-Chung HSU

Brief explanation

The abstract describes a method for designing circuits that takes into account the impact of different context parameters on the layout dependent effect of the circuit. The method involves identifying cells to be designed, identifying context parameters, generating abutment environments for each cell and context parameter, estimating the sensitivity of electrical properties of the cell to the context parameter, and determining key context parameters for static analysis of the circuit.

• The method identifies cells to be designed into a circuit.
• It identifies context parameters that affect the layout dependent effect of the circuit.
• Abutment environments are generated for each cell and context parameter.
• The sensitivity of electrical properties of the cell to the context parameter is estimated.
• Key context parameters for static analysis of the circuit are determined based on the sensitivity of the electrical properties and predetermined thresholds.

Potential Applications

• Circuit design for electronic devices
• Integrated circuit design
• Semiconductor manufacturing

Problems Solved

• Inaccurate circuit designs due to neglecting the impact of context parameters
• Inefficient circuit layouts that do not optimize for context parameters
• Difficulty in determining key context parameters for static analysis

Benefits

• More accurate and optimized circuit designs
• Improved performance and reliability of electronic devices
• Time and cost savings in circuit design and manufacturing processes

Abstract

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT DESIGN (18446739)

Main Inventor

Chin-Shen LIN

Brief explanation

The abstract of this patent application describes a method executed by a processor to optimize the power consumption of an integrated circuit (IC) layout diagram. The method involves determining a power parameter associated with a cell in the IC layout diagram and if the power parameter exceeds a design criterion, making modifications to the layout diagram such as altering the placement of the cell or modifying the power delivery path to the cell. The determination of the power parameter is done before the routing operation in the IC layout diagram.

• The method optimizes power consumption in an integrated circuit layout diagram.
• It determines a power parameter associated with a cell in the layout diagram.
• If the power parameter exceeds a design criterion, modifications are made to the layout diagram.
• Modifications can include altering the placement of the cell or modifying the power delivery path to the cell.
• The determination of the power parameter is done before the routing operation in the layout diagram.

Potential Applications

• This technology can be applied in the design and optimization of integrated circuits.
• It can be used in various industries that rely on integrated circuits, such as electronics, telecommunications, and computing.

Problems Solved

• Power consumption is a critical factor in the design of integrated circuits.
• This technology solves the problem of excessive power consumption by identifying cells with high power parameters and making necessary modifications to the layout diagram.

Benefits

• Optimizing power consumption improves the efficiency and performance of integrated circuits.
• By modifying the layout diagram, power delivery can be optimized, reducing power losses and improving overall circuit reliability.
• This method allows for proactive power optimization before the routing operation, saving time and resources in the design process.

Abstract

A method executed at least partially by a processor includes determining a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the method further includes performing a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The determining the power parameter is performed before a routing operation in the IC layout diagram.

REDUCED AREA STANDARD CELL ABUTMENT CONFIGURATIONS (18447187)

Main Inventor

Chi-Yu LU

Brief explanation

The patent application describes a method for designing a semiconductor device by analyzing the vertical abutment between two cell blocks and selecting a modified cell block to reduce any mismatch and spacing between them. The modified cell block has a continuous active region along an edge of the vertical abutment. The first standard cell block is replaced with the modified cell block to obtain a modified layout design.

• The method analyzes the vertical abutment between two cell blocks.
• If a mismatch is identified, a modified cell block is selected.
• The modified cell block reduces the mismatch and spacing between the two cell blocks.
• The modified cell block has a continuous active region along the edge of the vertical abutment.
• The first standard cell block is replaced with the modified cell block to obtain a modified layout design.

Potential Applications

This technology can be applied in the design and manufacturing of semiconductor devices, such as integrated circuits and microchips.

Problems Solved

1. Mismatch between standard cell blocks and cell blocks can cause issues in the design and manufacturing process of semiconductor devices. 2. Spacing between cell blocks can lead to inefficiencies and limitations in the overall design.

Benefits

1. The method reduces mismatches and spacing between cell blocks, improving the overall design and performance of semiconductor devices. 2. The continuous active region along the edge of the vertical abutment ensures better integration and connectivity between cell blocks. 3. The modified layout design obtained through this method can lead to more efficient and optimized semiconductor devices.

Abstract

A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

INTEGRATED CIRCUIT HAVING HYBRID SHEET STRUCTURE (18448136)

Main Inventor

Shang-Wei FANG

Brief explanation

The abstract describes an integrated circuit (IC) that includes nano-sheet structures and via structures for electrical connections. The IC has four nano-sheet structures with different widths and four via structures connected to them. The second width and the width of the second via structure are both greater than the third width and the width of the third via structure. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure, while the first and fourth via structures connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure.

• The integrated circuit (IC) includes nano-sheet structures and via structures for electrical connections.
• There are four nano-sheet structures with different widths and four via structures connected to them.
• The second width and the width of the second via structure are both greater than the third width and the width of the third via structure.
• The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures.
• The second and third via structures connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure.
• The first and fourth via structures connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure.

Potential Applications

This technology can be applied in various fields where integrated circuits are used, such as:

• Electronics manufacturing
• Telecommunications
• Computing devices
• Automotive industry

Problems Solved

The technology solves several problems in integrated circuit design and manufacturing, including:

• Efficient power distribution within the circuit
• Ensuring proper electrical connections between nano-sheet structures
• Optimizing circuit performance and reliability

Benefits

The benefits of this technology include:

• Improved power distribution efficiency
• Enhanced circuit performance and reliability
• Simplified design and manufacturing processes
• Potential for smaller and more compact integrated circuits.

Abstract

An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM (18362842)

Main Inventor

Kam-Tou SIO

Brief explanation

The abstract describes a method for generating a layout diagram for an integrated circuit. The method involves arranging multiple cells in the layout diagram, where each cell has power rails along its boundaries. The cells are placed in a specific direction, and cell pins are positioned over selected via placement points in one of the cells, following a design rule. The cell pins have one end spaced from both power rails in the specified direction.

• The method involves arranging cells in a layout diagram for an integrated circuit.
• Each cell in the layout diagram has power rails along its boundaries.
• The cells are placed in a specific direction, with one boundary spaced from the other boundary.
• Cell pins are positioned over selected via placement points in one of the cells.
• The placement of cell pins follows a design rule.
• The cell pins have one end spaced from both power rails in the specified direction.

Potential Applications

• This method can be used in the design and layout of integrated circuits.
• It can be applied in various industries that utilize integrated circuits, such as electronics, telecommunications, and computing.

Problems Solved

• The method provides a systematic approach to generating layout diagrams for integrated circuits.
• It ensures proper placement of cells and cell pins, following design rules.
• The method helps in optimizing the layout for efficient power distribution and signal routing.

Benefits

• The method allows for the efficient arrangement of cells in an integrated circuit layout.
• It ensures proper spacing between power rails and cell pins, reducing the risk of electrical interference.
• The systematic approach helps in improving the overall performance and reliability of the integrated circuit.

Abstract

A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.

OPTICAL SENSOR AND METHODS OF MAKING THE SAME (18232756)

Main Inventor

You-Cheng JHANG

Brief explanation

The abstract describes optical sensors and their manufacturing methods. It specifically mentions a sensing apparatus consisting of an image sensor, a collimator with an array of apertures, and an optical filtering layer.

• The sensing apparatus includes an image sensor, collimator, and optical filtering layer.
• The collimator has an array of apertures.
• The optical filtering layer filters a portion of light transmitted into the array of apertures.

Potential Applications

This technology has potential applications in various fields, including:

• Imaging devices: The sensing apparatus can be used in cameras, smartphones, and other imaging devices to improve image quality and filtering capabilities.
• Medical equipment: Optical sensors with filtering capabilities can be used in medical equipment for diagnostic imaging, such as endoscopes or ultrasound devices.
• Environmental monitoring: The sensing apparatus can be utilized in environmental monitoring systems to analyze and filter specific wavelengths of light for various purposes, such as pollution detection or plant health monitoring.

Problems Solved

The technology addresses several problems related to optical sensing:

• Light filtering: The optical filtering layer solves the problem of selectively filtering specific wavelengths of light, allowing for improved image quality and analysis.
• Aperture array: The collimator's array of apertures helps in controlling the direction and intensity of light entering the image sensor, reducing unwanted noise and improving accuracy.
• Manufacturing efficiency: The patent application may describe manufacturing methods that improve the efficiency and precision of producing optical sensors with collimators and filtering layers.

Benefits

The technology offers several benefits:

• Enhanced image quality: By filtering out unwanted light, the sensing apparatus can produce clearer and more accurate images.
• Improved signal-to-noise ratio: The collimator and filtering layer help reduce noise and improve the signal-to-noise ratio, resulting in better data analysis and interpretation.
• Versatile applications: The technology can be applied in various fields, allowing for diverse applications in imaging, medical equipment, and environmental monitoring.

Abstract

Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.

MEMORY DEVICE (18451946)

Main Inventor

CHIEN-AN LAI

Brief explanation

The patent application describes a memory device that consists of multiple cells arranged in a matrix. Each cell is connected to a bit line, and a voltage control circuit is connected to a selected bit line. The voltage control circuit includes a voltage detection circuit that detects the supply voltage and a voltage source selection circuit that selects a voltage source based on the detected supply voltage. The selected voltage source is then connected to the bit line to provide a write voltage.

• The memory device includes multiple cells arranged in a matrix.
• Each cell is connected to a bit line.
• The voltage control circuit is connected to a selected bit line.
• The voltage detection circuit detects the instantaneous supply voltage.
• The voltage source selection circuit selects a voltage source based on the detected supply voltage.
• A switch connects the selected voltage source to the selected bit line to provide a write voltage.

Potential Applications:

• This memory device can be used in various electronic devices such as computers, smartphones, and tablets.
• It can be utilized in data storage systems, allowing for efficient and reliable data storage and retrieval.

Problems Solved:

• The voltage control circuit ensures that the appropriate voltage source is selected based on the detected supply voltage, preventing any potential damage to the memory device.
• The use of multiple cells arranged in a matrix allows for a higher storage capacity and faster data access.

Benefits:

• The memory device provides efficient and reliable data storage and retrieval.
• The voltage control circuit ensures the safety and longevity of the memory device.
• The use of multiple cells arranged in a matrix allows for a higher storage capacity and faster data access.

Abstract

A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

MEMORY CIRCUIT AND METHOD OF OPERATING SAME (18362952)

Main Inventor

Meng-Sheng CHANG

Brief explanation

The abstract describes a method of operating a memory circuit that involves turning on and off programming and selection devices to control the flow of current through fuse elements. 

• The method involves turning on a first programming device and a first selection device, causing a current to flow through a first fuse element.
• The first fuse element is connected between the first selection device and the first programming device.
• The method also includes turning off a second programming device and a second selection device.
• The second fuse element, which is connected between the second selection device and the first programming device, is blocked from the flow of current.

Potential applications of this technology:

• Memory circuits in electronic devices such as computers, smartphones, and tablets.
• Data storage systems in cloud computing and data centers.
• Integrated circuits used in various electronic devices.

Problems solved by this technology:

• Efficient control of current flow through fuse elements in memory circuits.
• Preventing unwanted current flow through specific fuse elements.
• Ensuring accurate programming and selection of fuse elements.

Benefits of this technology:

• Improved reliability and performance of memory circuits.
• Enhanced data storage and retrieval capabilities.
• Efficient use of power and resources in memory circuits.

Abstract

A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.

HEAT CONTROLLED SWITCH (17834944)

Main Inventor

Yu-Wei Ting

Brief explanation

The patent application describes a semiconductor device that includes a heater element, a conductor material with programmable conductivity, and an insulator layer. The device can be programmed by applying voltage differences to the heater element and conductor material, controlling the capacitance between them.

• The semiconductor device has a heater element that generates heat when current flows through it.
• A conductor material with programmable conductivity is included in the device.
• An insulator layer separates the heater element and conductor material.
• The conductor material can be programmed by applying voltage differences to it and the heater element.
• The voltage differences control the capacitance between the conductor material and heater element.
• The capacitance is lower when the conductor material is being programmed compared to when it is not being programmed.

Potential Applications

• This technology can be used in electronic devices that require precise control over capacitance.
• It can be applied in sensors, actuators, and other devices that rely on programmable conductivity.
• The semiconductor device can be used in communication systems, computing devices, and various other electronic applications.

Problems Solved

• The technology solves the problem of controlling capacitance in semiconductor devices.
• It provides a solution for programming the conductivity of a conductor material.
• The device offers a way to adjust capacitance based on the programming state of the conductor material.

Benefits

• The semiconductor device allows for precise control over capacitance, enhancing the performance of electronic devices.
• The programmable conductivity of the conductor material provides flexibility in device design and functionality.
• The technology offers a cost-effective solution for adjusting capacitance in semiconductor devices.

Abstract

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (17838246)

Main Inventor

Chin-Ta CHEN

Brief explanation

The patent application describes a method for forming metal vias in a semiconductor substrate. Here are the key points:

• A dielectric layer is deposited over the semiconductor substrate.
• A first photoresist layer is formed over the dielectric layer.
• The first photoresist layer is patterned to create through holes.
• The height of the first photoresist layer varies between different through holes.
• A spacer is formed on the lower portion of the first photoresist layer.
• An etching process is performed on the dielectric layer to create via holes, with the spacer protecting the lower portion of the first photoresist layer.
• Metal vias are formed in the via holes.

Potential applications of this technology:

• Integrated circuits manufacturing
• Semiconductor device fabrication

Problems solved by this technology:

• Efficient formation of metal vias in a semiconductor substrate
• Improved control over the height of the first photoresist layer

Benefits of this technology:

• Enhanced precision and accuracy in the formation of metal vias
• Cost-effective manufacturing process for integrated circuits
• Improved performance and reliability of semiconductor devices.

Abstract

A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME (17838253)

Main Inventor

Yan-Ming Tsai

Brief explanation

The patent application describes a method of forming a semiconductor device. Here are the key points:

• The method involves providing a substrate with a gate stack, an epitaxial layer, and a dielectric layer.
• An opening is formed through the dielectric layer to expose the epitaxial layer.
• A metal silicon-germanide layer is formed on the exposed epitaxial layer. The metal used in this layer has a high melting point of about 1700°C or higher.
• A connector is then formed over the metal silicon-germanide layer in the opening.

Potential applications of this technology:

• This method can be used in the manufacturing of various semiconductor devices, such as transistors, integrated circuits, and memory devices.
• It can be applied in industries that rely on semiconductor technology, including electronics, telecommunications, and computing.

Problems solved by this technology:

• The use of a metal silicon-germanide layer with a high melting point provides improved thermal stability and reliability to the semiconductor device.
• The method allows for the formation of a reliable and robust connection between the metal silicon-germanide layer and the connector.

Benefits of this technology:

• The high melting point metal silicon-germanide layer ensures the stability of the semiconductor device under high-temperature conditions.
• The reliable connection formed by the connector enhances the overall performance and longevity of the semiconductor device.
• This method offers a more efficient and cost-effective way of manufacturing semiconductor devices with improved thermal properties.

Abstract

A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.

METHOD FOR FABRICATING MASK (17836820)

Main Inventor

Ping-Hsun LIN

Brief explanation

The abstract describes a method for fabricating a mask, which involves depositing a target layer on a dielectric substrate and forming a patterned photoresist layer based on an integrated circuit (IC) layout. The method also includes determining dry etch control parameters based on the material of the target layer and the IC layout, and using a dry etcher to etch the target layer through the patterned photoresist layer.

• The method involves depositing a target layer on a dielectric substrate.
• A patterned photoresist layer is formed based on an integrated circuit (IC) layout.
• Dry etch control parameters are determined based on the material of the target layer and the IC layout.
• A dry etcher is used to etch the target layer through the patterned photoresist layer.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication
• Mask production for photolithography processes

Problems Solved

• Provides a method for fabricating masks with precise patterns for use in semiconductor manufacturing and integrated circuit fabrication.
• Enables efficient and accurate etching of target layers based on the specific material and layout requirements.

Benefits

• Allows for the production of high-quality masks with precise patterns.
• Enhances the efficiency and accuracy of the etching process.
• Enables the fabrication of complex integrated circuits with improved performance.

Abstract

A method for fabricating a mask is provided. The method includes depositing a target layer over a dielectric substrate; forming a patterned photoresist layer over the target layer according to an integrated circuit (IC) layout; determining a plurality of dry etch control parameters according a material of the target layer and an information of the IC layout; and using a dry etcher set up with the dry etch control parameters, etching the target layer through the patterned photoresist layer.

SELECTIVE ETCHING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURED USING THE SAME (17836452)

Main Inventor

Kuan-Da HUANG

Brief explanation

The patent application describes a method for manufacturing a semiconductor structure. Here is a simplified explanation of the abstract:

• The method involves forming a semiconductor portion with an exposed region.
• Two fin sidewalls, made of a dielectric material, are formed on opposite sides of the exposed region.
• An etching process is performed to remove the exposed region and create a recess.
• During the etching process, a protection layer is formed to safeguard each fin sidewall.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Integrated circuit fabrication
• Electronic device production

Problems solved by this technology:

• Protecting the fin sidewalls during the etching process
• Ensuring precise and controlled etching of the exposed region
• Preventing damage to the semiconductor structure during manufacturing

Benefits of this technology:

• Improved manufacturing efficiency and accuracy
• Enhanced protection of delicate fin sidewalls
• Enables the creation of complex semiconductor structures with recessed regions

Abstract

A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

METHOD FOR FILLING TRENCH IN SEMICONDUCTOR DEVICE (17836463)

Main Inventor

Kenichi SANO

Brief explanation

The patent application describes a method for coating a semiconductor structure in a semiconductor device using a multi-step procedure. Here are the key points:

• The method involves applying a first solution containing a metal-containing solute onto the semiconductor structure, which includes a feature and a trench.
• The first solution forms a first coating that covers both the feature and the trench.
• The first coating is then heated in a multi-step procedure, starting at a first temperature and then increasing to a second temperature that is not lower than the first temperature.
• This heating process transforms the first coating into a first film.
• Next, a second solution containing the same metal-containing solute is applied onto the first film to form a second coating.
• Similar to the first coating, the second coating is heated in a multi-step procedure, starting at a third temperature and then increasing to a fourth temperature that is not lower than the third temperature.
• This heating process transforms the second coating into a second film.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit fabrication

Problems solved by this technology:

• Provides a method for coating semiconductor structures with a metal-containing solute, ensuring uniform coverage over features and trenches.
• Enables the formation of films through a multi-step heating procedure, enhancing the stability and durability of the coatings.

Benefits of this technology:

• Improved coating process for semiconductor structures, leading to enhanced performance and reliability of semiconductor devices.
• Enables the creation of uniform and durable films, reducing the risk of defects and improving overall device functionality.

Abstract

A method includes: applying a first solution to a semiconductor structure of a semiconductor device to form a first coating, the semiconductor structure including a feature and the trench, the first coating being formed in the trench and over the feature, the first solution containing a metal-containing solute; heating the first coating in a multi-step procedure to turn the first coating into a first film, the multi-step procedure including heating at a first temperature, followed by heating at a second temperature not lower than the first temperature; applying a second solution onto the first film to form a second coating, the second solution containing the metal-containing solute; and heating the second coating in a multi-step procedure to turn the second coating into a second film, the multi-step procedure including heating at a third temperature, followed by heating at a fourth temperature not lower than the third temperature.

CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE (18447539)

Main Inventor

Po-Hsien CHENG

Brief explanation

The patent application describes a method of reducing contact resistance and improving electrical performance in electronic devices by using a layer of carbon at a metal interface. This carbon layer can be made of graphite or graphene and is placed between different metal components in the device. 

• The layer of carbon reduces contact resistance at the metal interface, improving electrical performance.
• It can also prevent heat transfer from one metal to another during deposition, resulting in more symmetric deposition of the second metal and reducing surface roughness.
• In some cases, the layer of carbon is etched before deposition of the second metal to further reduce contact resistance at the metal interface.

Potential Applications

• This technology can be applied in various electronic devices, such as integrated circuits, transistors, and other semiconductor devices.
• It can be used in the manufacturing of computer processors, memory chips, and other electronic components.

Problems Solved

• Contact resistance at metal interfaces can hinder the electrical performance of electronic devices.
• Uneven deposition of metal layers can lead to surface roughness and increased contact resistance.

Benefits

• Improved electrical performance of electronic devices.
• Reduced contact resistance at metal interfaces.
• More symmetric deposition of metal layers, resulting in reduced surface roughness.

Abstract

A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

DICING METHOD FOR STACKED SEMICONDUCTOR DEVICES (18447581)

Main Inventor

Tsung-Hsing Lu

Brief explanation

The patent application describes a semiconductor structure consisting of two devices bonded together. The first device has two sidewalls, one facing away from the second device and one facing towards it. The second device also has two sidewalls, one facing towards the first device and one facing away from it. The surface roughness of the second sidewall of the first device is greater than that of the first sidewall, and the surface roughness of the fourth sidewall of the second device is greater than that of the third sidewall.

• The semiconductor structure includes two devices bonded together.
• The first device has a sidewall facing away from the second device, and a sidewall facing towards the second device.
• The second device has a sidewall facing towards the first device, and a sidewall facing away from the first device.
• The surface roughness of the second sidewall of the first device is larger than the surface roughness of the first sidewall.
• The surface roughness of the fourth sidewall of the second device is larger than the surface roughness of the third sidewall.

Potential Applications

• Semiconductor manufacturing
• Electronics industry
• Integrated circuits

Problems Solved

• Improved bonding between semiconductor devices
• Enhanced performance of semiconductor structures

Benefits

• Increased surface roughness for better bonding
• Improved overall performance of the semiconductor structure

Abstract

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING (18366864)

Main Inventor

Hung-Yao Chen

Brief explanation

The patent application describes a method for forming two fins made of different materials within an insulation material over a substrate. The first fin has a certain width and the second fin has a different width. 

• The method involves creating two fins made of different materials within an insulation material over a substrate.
• The first fin and the second fin are separated by the insulation material.
• The first fin has a specific width, while the second fin has a different width.
• A first capping layer is formed over the first fin, and a second capping layer is formed over the second fin.
• The first capping layer has a certain thickness, while the second capping layer has a different thickness.

Potential applications of this technology:

• Semiconductor manufacturing: This method can be used in the production of semiconductor devices, where the different materials in the fins can enhance performance or enable specific functionalities.
• Nanoelectronics: The ability to create fins with different materials and widths can be utilized in the development of nanoelectronic devices, allowing for improved control and performance.
• Energy storage: The method may find applications in the production of energy storage devices, such as batteries or supercapacitors, where the different materials in the fins can optimize energy storage and release.

Problems solved by this technology:

• Material optimization: By allowing for the use of different materials in the fins, this method enables the selection of materials that are best suited for specific purposes, improving overall device performance.
• Design flexibility: The ability to vary the width of the fins provides greater design flexibility, allowing for the customization of devices to meet specific requirements.
• Enhanced functionality: The use of different materials and widths in the fins can enable the incorporation of additional functionalities into devices, expanding their capabilities.

Benefits of this technology:

• Improved performance: The ability to use different materials and widths in the fins can enhance device performance, such as speed, power efficiency, or energy storage capacity.
• Customization: The method allows for the customization of devices by varying the materials and widths of the fins, enabling the development of tailored solutions for specific applications.
• Versatility: The technology can be applied to various fields, including semiconductor manufacturing, nanoelectronics, and energy storage, providing versatility in its potential applications.

Abstract

In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first t

MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING (18230664)

Main Inventor

Feng-Chien Hsieh

Brief explanation

The patent application describes a method of manufacturing a semiconductor wafer. Here is a simplified explanation of the abstract:

• The method involves exposing the semiconductor wafer to dopant species, which are substances that introduce impurities into the semiconductor material.
• This exposure forms one or more first implant layers on the semiconductor wafer.
• The geometric parameter values of the first implant layers are then tested.
• Based on the test results, the semiconductor wafer is conditionally exposed to additional dopant species to form one or more additional implant layers.
• After forming the additional implant layers, one or more additional circuit layers are conditionally formed on the semiconductor wafer, resulting in the creation of multiple functional electronic circuits.
• Finally, the semiconductor wafer is conditionally tested using a wafer acceptance test (WAT) operation.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Electronics manufacturing industry

Problems solved by this technology:

• Provides a method for manufacturing semiconductor wafers with multiple functional electronic circuits.
• Allows for conditional exposure to dopant species based on the test results of the first implant layers, ensuring optimal performance of the circuits.

Benefits of this technology:

• Efficient manufacturing process for semiconductor wafers with multiple circuits.
• Improved quality control through conditional testing and exposure to dopant species.
• Enables the production of high-performance electronic devices.

Abstract

A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures (17839292)

Main Inventor

Shan-Yu Huang

Brief explanation

==Abstract==

The patent application describes a structure that includes two dies with transistors and conductive elements that interconnect them. The dies are surrounded by seal rings for protection.

Patent/Innovation Explanation

• The structure includes two dies with transistors.
• Each die is surrounded by a seal ring in the top view.
• Conductive elements extend into both dies and interconnect them.
• A third seal ring surrounds both dies and the conductive elements.

Potential Applications

• Integrated circuits
• Semiconductor devices
• Electronics manufacturing

Problems Solved

• Provides a structure for interconnecting multiple dies in a compact manner.
• Protects the dies and conductive elements with seal rings.

Benefits

• Enables efficient integration of multiple dies in a single structure.
• Enhances the reliability and durability of the interconnected dies.
• Simplifies the manufacturing process for electronic devices.

Abstract

A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.

Molding Structures for Integrated Circuit Packages and Methods of Forming the Same (17840362)

Main Inventor

Shu-Shen Yeh

Brief explanation

The abstract describes a method for forming a semiconductor device. Here is a simplified explanation of the abstract:

• The method involves attaching an integrated circuit die to an interposer, which is a substrate that provides electrical connections.
• An encapsulant is formed over the interposer and around the integrated circuit die. The top surface of the encapsulant and the top surface of the integrated circuit die are level, meaning they are at the same height.
• Recesses are then formed in the encapsulant, which are depressions or cavities in the material.
• Finally, the interposer is bonded to a package substrate, which is a larger substrate that provides further electrical connections. The recesses are positioned along the outer edge of the encapsulant after the bonding process.

Potential applications of this technology:

• Semiconductor devices manufacturing
• Electronics industry

Problems solved by this technology:

• Ensures a level surface between the encapsulant and the integrated circuit die, which can improve the overall performance and reliability of the semiconductor device.
• The recesses along the outer edge of the encapsulant provide additional space for electrical connections and can help in reducing the overall size of the device.

Benefits of this technology:

• Improved performance and reliability of semiconductor devices.
• Reduction in size of the device, allowing for more compact and efficient designs.
• Enhanced electrical connections and signal transmission due to the recesses in the encapsulant.

Abstract

In an embodiment, a method of forming a semiconductor device includes: attaching an integrated circuit die to an interposer; forming an encapsulant over the interposer and around the integrated circuit die, a top surface of the encapsulant and a top surface of the integrated circuit die being level; forming recesses in the encapsulant; and bonding the interposer to a package substrate, wherein after bonding the interposer to the package substrate, each of the recesses being along an outer edge of the encapsulant.

SEMICONDUCTOR DEVICE (17746990)

Main Inventor

Yu-Hung Lin

Brief explanation

The patent application describes a semiconductor device that includes two semiconductor dies, thermal silicon substrates, and an encapsulation. The second semiconductor die is placed on top of and connected to the first semiconductor die. The thermal silicon substrates are positioned on the first semiconductor die, but they are separated from the second semiconductor die. The encapsulation covers both the second semiconductor die and the thermal silicon substrates. It consists of a filling material layer and an insulator. The filling material layer is located between the second semiconductor die and the thermal silicon substrates, and it is separated from them by the insulator.

• The semiconductor device includes two semiconductor dies, thermal silicon substrates, and an encapsulation.
• The second semiconductor die is placed on top of and connected to the first semiconductor die.
• The thermal silicon substrates are positioned on the first semiconductor die but are separated from the second semiconductor die.
• The encapsulation covers both the second semiconductor die and the thermal silicon substrates.
• The encapsulation consists of a filling material layer and an insulator.
• The filling material layer is located between the second semiconductor die and the thermal silicon substrates.
• The filling material layer is separated from the second semiconductor die and the thermal silicon substrates by the insulator.

Potential Applications

This technology could be applied in various semiconductor devices, such as integrated circuits, microprocessors, and memory chips.

Problems Solved

The semiconductor device addresses the issue of thermal management by using thermal silicon substrates to dissipate heat effectively.

Benefits

The use of thermal silicon substrates helps in efficient heat dissipation, preventing overheating and improving the overall performance and reliability of the semiconductor device.

Abstract

A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.

Semiconductor Package and Method (17806532)

Main Inventor

Chen Chiang Yu

Brief explanation

The abstract describes a semiconductor package with a cooling system and a method of forming it. The package includes an interposer, package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the package components. The cooling system consists of metal layers on top surfaces of the package components, first metal pins on the metal layers, second metal pins bonded to the first metal pins with solder, and a lid with openings over the second metal pins.

• The semiconductor package includes a cooling system to prevent overheating of the components.
• The cooling system consists of metal layers, metal pins, and a lid with openings.
• The metal layers are placed on top surfaces of the package components.
• First metal pins are attached to the metal layers.
• Second metal pins are bonded to the first metal pins using solder.
• A lid with openings is placed over the second metal pins.

Potential Applications

• This semiconductor package with a cooling system can be used in various electronic devices, such as computers, smartphones, and gaming consoles.
• It can be particularly beneficial in high-performance devices that generate a lot of heat.

Problems Solved

• Overheating is a common issue in electronic devices, which can lead to reduced performance and even component failure.
• This technology solves the problem of overheating by providing an effective cooling system for the semiconductor package.

Benefits

• The cooling system helps to maintain optimal operating temperatures for the semiconductor components, ensuring their performance and longevity.
• The use of metal layers and pins improves heat dissipation, enhancing the overall cooling efficiency.
• The encapsulant and lid provide protection to the package components while allowing for effective heat transfer.

Abstract

A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.

HEAT DISSIPATION STRUCTURES FOR INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME (17837312)

Main Inventor

Szu-Wei Lu

Brief explanation

The patent application describes a device that includes a package substrate, an interposer, a die, a ring, a molding compound, and thermal-conductive layers. Here are the key points:

• The device consists of a package substrate, which serves as a base for the other components.
• An interposer is bonded to one side of the package substrate.
• A die is bonded to the other side of the interposer.
• A ring is present on the package substrate, surrounding the interposer and the die.
• A molding compound is placed between the ring and the die, making physical contact with the ring.
• A plurality of thermal-conductive layers are placed over the molding compound and the die, with the molding compound acting as a barrier between the layers and the ring.

Potential applications of this technology:

• This device can be used in electronic devices that require efficient thermal management, such as high-performance computers, servers, and power electronics.
• It can also be utilized in automotive applications, where heat dissipation is crucial for the proper functioning of electronic components.

Problems solved by this technology:

• The device addresses the issue of thermal management by providing a structure that allows for efficient heat transfer from the die to the thermal-conductive layers.
• The presence of the molding compound between the thermal-conductive layers and the ring helps prevent any interference or heat loss.

Benefits of this technology:

• The device offers improved thermal conductivity, allowing for better heat dissipation and preventing overheating of the die.
• The use of the interposer and the molding compound helps reduce the thermal resistance between the die and the thermal-conductive layers, enhancing overall thermal performance.
• The design of the device provides a compact and efficient solution for thermal management in electronic devices.

Abstract

A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, where the ring surrounds the first die and the interposer, a molding compound disposed between the ring and the first die, where the molding compound is in physical contact with the ring, and a plurality of thermal-conductive layers over and in physical contact with the molding compound and the first die, where the molding compound is disposed between the plurality of thermal-conductive layers and the ring.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING REDISTRIBUTION STRUCTURES OF CONDUCTIVE ELEMENTS (17835776)

Main Inventor

Ho Che Yu

Brief explanation

The abstract describes a semiconductor device and its manufacturing method. Here is a simplified explanation of the abstract:

• The invention involves a semiconductor device that consists of a first semiconductor die placed on a first redistribution structure.
• On the opposite side of the first redistribution structure, a second redistribution structure is placed.
• Additionally, a third redistribution structure is placed on the opposite surface of the semiconductor die as the first redistribution structure.
• Through via structures are used to connect at least one of the redistribution structures to the active surface of the semiconductor die.

Potential applications of this technology:

• This semiconductor device and manufacturing method can be used in various electronic devices such as smartphones, computers, and other consumer electronics.
• It can also be applied in industrial applications such as automation systems, robotics, and automotive electronics.

Problems solved by this technology:

• The invention solves the problem of connecting redistribution structures to the active surface of a semiconductor die.
• It provides a reliable and efficient method for connecting different components of a semiconductor device.

Benefits of this technology:

• The use of through via structures allows for efficient and reliable connections between redistribution structures and the active surface of the semiconductor die.
• The manufacturing method described in the patent application provides a cost-effective solution for producing semiconductor devices with improved connectivity.
• The invention enables the development of smaller and more compact electronic devices without compromising performance.

Abstract

A semiconductor device and method of manufacture in which a first semiconductor die is disposed along a first redistribution structure, and a second redistribution structure is disposed along an opposite side of the first redistribution structure. A third redistribution structure may be disposed along an opposite surface of the semiconductor die as the first redistribution structure. Through via structures pass through at least the first redistribution structure to connect at least one of the redistribution structures to an active surface of the semiconductor die.

SEMICONDUCTOR DEVICE INCLUDING METAL SURROUNDING VIA CONTACT AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE (17836781)

Main Inventor

Shuen-Shin LIANG

Brief explanation

The abstract describes a semiconductor device that includes various layers and structures for improved performance and connectivity. Here is a simplified explanation of the abstract:

• The semiconductor device consists of a substrate, which serves as the foundation.
• A source/drain region is embedded in the substrate, providing electrical connections.
• A silicide structure is placed on top of the source/drain region, enhancing conductivity.
• A first dielectric layer is added over the substrate, providing insulation.
• A conductive contact is inserted into the first dielectric layer, positioned above the silicide structure.
• A second dielectric layer is applied over the first dielectric layer, providing additional insulation.
• A via contact is placed in the second dielectric layer, connecting to the conductive contact.
• A first metal surrounds the via contact, further enhancing connectivity.

Potential applications of this technology:

• Integrated circuits: The semiconductor device can be used in the production of integrated circuits, enabling improved performance and connectivity.
• Microprocessors: The technology can be implemented in microprocessors, enhancing their functionality and efficiency.
• Memory devices: The semiconductor device can be utilized in memory devices, improving their speed and reliability.

Problems solved by this technology:

• Enhanced conductivity: The addition of the silicide structure improves the conductivity of the source/drain region, leading to better electrical connections.
• Improved insulation: The use of multiple dielectric layers provides better insulation between different components, reducing the risk of electrical interference.

Benefits of this technology:

• Increased performance: The improved conductivity and insulation result in enhanced performance of the semiconductor device.
• Better connectivity: The various layers and structures enable more efficient and reliable electrical connections.
• Higher efficiency: The technology allows for more efficient use of electrical energy, leading to improved overall efficiency of the device.

Abstract

A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.

SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS (18447682)

Main Inventor

Wei-Ling CHANG

Brief explanation

The patent application describes a method for fabricating semiconductor structures and gate-conductors to create a circuit cell. It involves patterning metal layers to form horizontal and vertical conducting lines, which are connected through pin-connectors.

• The method involves fabricating semiconductor structures and gate-conductors.
• Metal layers are patterned to create horizontal and vertical conducting lines.
• Vertical conducting lines are aligned with gate-conductors and circuit cell boundaries.
• Pin-connectors directly connect vertical and horizontal conducting lines.

Potential Applications

This technology can be applied in various fields that utilize semiconductor devices, such as:

• Integrated circuits
• Microprocessors
• Memory devices
• Power electronics

Problems Solved

The technology addresses the following problems in semiconductor fabrication:

• Efficiently connecting vertical and horizontal conducting lines.
• Aligning vertical conducting lines with gate-conductors and circuit cell boundaries.
• Simplifying the fabrication process.

Benefits

The use of this technology offers several benefits:

• Improved electrical connectivity between vertical and horizontal conducting lines.
• Enhanced alignment accuracy between vertical conducting lines and gate-conductors.
• Streamlined fabrication process for semiconductor structures.
• Potential for increased performance and reliability of semiconductor devices.

Abstract

A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

GRAPHENE-METAL HYBRID INTERCONNECT (17835924)

Main Inventor

Jian-Hong LIN

Brief explanation

The abstract describes a patent application related to improving the performance of interconnects in integrated circuits by leveraging the material properties of graphene. The application proposes different methods for incorporating graphene into the bulk metal layer of interconnects to create a hybrid metal/graphene structure.

• The first method involves alternating the metal fill process with graphene deposition to create a composite graphene matrix within a copper damascene layer.
• The second method suggests implanting carbon atoms into a surface layer of metal to embed graphene.
• The third method involves dispersing graphene flakes in a damascene copper plating solution to create a distributed graphene matrix.

These methods can be used individually or in combination to enhance the conductivity of interconnects.

Potential Applications

• Improved performance of interconnects in integrated circuits.
• Enhanced conductivity in electronic devices.

Problems Solved

• Challenges in depositing graphene onto a copper surface.
• Enhancing the conductivity of interconnects.

Benefits

• Improved performance and efficiency of integrated circuits.
• Enhanced conductivity leads to faster data transfer and reduced power consumption.

Abstract

Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.

GRAPHENE-CLAD METAL INTERCONNECT (17837664)

Main Inventor

Jian-Hong LIN

Brief explanation

The abstract of the patent application describes a technology that uses graphene-clad metal interconnects to improve the performance of interconnect structures in integrated circuits. Here are the key points:

• Graphene-clad metal interconnects are used in both damascene and patterned interconnect structures at lower metal layers.
• This technology reduces resistance in interconnects by extending the material properties of graphene to the metal layers.
• The graphene cladding can be used with or without a metal barrier/liner.
• If a metal barrier/liner is present, it can catalyze the growth of an overlying graphene layer.
• Graphene can also be selectively grown on barrier surfaces.
• The patent application describes fully integrated structures and process flows for integrated circuits with graphene-clad metallization.

Potential applications of this technology:

• Integrated circuits and electronic devices that require high-performance interconnects.
• Graphene-clad metal interconnects can be used in various industries, including telecommunications, computing, and consumer electronics.

Problems solved by this technology:

• Resistance in interconnects is a common issue in integrated circuits, leading to reduced performance and increased power consumption.
• This technology addresses the problem of high resistance by utilizing graphene-clad metal interconnects, which have improved conductivity.

Benefits of this technology:

• Significant reductions in resistance in interconnect structures, leading to improved performance and lower power consumption in integrated circuits.
• The use of graphene-clad metal interconnects extends the material properties of graphene to the metal layers, enhancing conductivity.
• The technology provides flexibility in the use of metal barriers/liners, allowing for catalysis of graphene growth or selective growth on barrier surfaces.

Abstract

A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.

SEMICONDUCTOR DEVICE INCLUDING DIELECTRICS MADE OF POROUS ORGANIC FRAMEWORKS, AND METHOD OF FABRICATING THE SAME (17839447)

Main Inventor

Szu-Hua Chen

Brief explanation

The patent application describes a semiconductor device that includes a substrate and an interconnection layer. The interconnection layer consists of multiple etch-stop layers, first dielectric layers, and conductive layers. The first dielectric layers are made of porous organic framework (POF) materials with a low dielectric constant and high thermal conductivity. The conductive layers are embedded within the first dielectric layers.

• The interconnection layer of the semiconductor device includes multiple etch-stop layers, first dielectric layers, and conductive layers.
• The first dielectric layers are made of porous organic framework (POF) materials.
• The POF dielectrics have a low dielectric constant of 2 or less.
• The POF dielectrics have a high thermal conductivity of 1 W/(m·K) or more.
• The conductive layers are embedded within the first dielectric layers.

Potential Applications

• This technology can be applied in the manufacturing of various semiconductor devices, such as integrated circuits, microprocessors, and memory chips.
• It can be used in the development of high-performance electronic devices that require efficient heat dissipation and low power consumption.

Problems Solved

• Traditional semiconductor devices often face challenges related to heat dissipation and power consumption.
• The use of POF dielectrics with high thermal conductivity helps to address these issues by improving heat transfer and reducing power consumption.

Benefits

• The use of POF dielectrics with a low dielectric constant allows for better signal integrity and reduced signal loss in the interconnection layer.
• The high thermal conductivity of the POF dielectrics helps in efficient heat dissipation, preventing overheating and improving the overall performance and reliability of the semiconductor device.
• The embedded conductive layers within the POF dielectrics provide enhanced electrical conductivity and connectivity within the interconnection layer.

Abstract

A semiconductor device includes a substrate and an interconnection layer disposed on the substrate. The interconnection layer includes a plurality of etch-stop layers, a plurality of first dielectric layers, and a plurality of conductive layers. The first dielectric layers are disposed on the plurality of etch-stop layers, wherein the plurality of first dielectric layers comprises porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The conductive layers are embedded in the first dielectric layers.

Semiconductor Package and Method (17663683)

Main Inventor

Shu-Shen Yeh

Brief explanation

The abstract describes a semiconductor package with a recessed stiffener ring and a method of forming it. The package includes a substrate, a semiconductor die bonded to the substrate, an underfill between the die and substrate, and a stiffener ring attached to the substrate that encircles the die in a top view. The stiffener ring has a recess facing the die.

• The semiconductor package includes a substrate, semiconductor die, underfill, and stiffener ring.
• The stiffener ring is attached to the substrate and encircles the semiconductor die.
• The stiffener ring has a recess that faces the semiconductor die.

Potential Applications:

• This technology can be used in various electronic devices that require semiconductor packages, such as smartphones, tablets, computers, and other consumer electronics.
• It can also be applied in industrial applications where semiconductor packages are used, such as automotive electronics, aerospace systems, and medical devices.

Problems Solved:

• The recessed stiffener ring helps to provide additional support and protection to the semiconductor die, reducing the risk of damage during handling, transportation, and operation.
• It helps to improve the overall reliability and durability of the semiconductor package.

Benefits:

• The recessed stiffener ring enhances the structural integrity of the semiconductor package, reducing the risk of failure due to mechanical stress or impact.
• It allows for better thermal management by providing a pathway for heat dissipation from the semiconductor die.
• The recessed design also helps to minimize the overall package size, making it more compact and suitable for space-constrained applications.

Abstract

A semiconductor package including a recessed stiffener ring and a method of forming are provided. The semiconductor package may include a substrate, a semiconductor die bonded to the substrate, an underfill between the semiconductor die and the substrate, and a stiffener ring attached to the substrate, wherein the stiffener ring encircles the semiconductor die in a top view. The stiffener ring may include a recess that faces the semiconductor die.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (17746822)

Main Inventor

Hsien-Wei Chen

Brief explanation

The abstract describes a semiconductor package that includes an interconnect structure, multiple dies arranged side by side on the structure, an underfill material filling the lower part of the gap between adjacent dies, a conductive layer covering the back surfaces of the adjacent dies and filling the upper part of the gap, and an encapsulating material surrounding the dies and conductive layer.

• The semiconductor package includes an interconnect structure and multiple dies arranged side by side.
• An underfill material fills the lower part of the gap between adjacent dies, providing structural support.
• A conductive layer covers the back surfaces of the adjacent dies and fills the upper part of the gap, enhancing electrical connectivity.
• An encapsulating material surrounds the dies and conductive layer, providing protection and stability.

Potential Applications

• This technology can be applied in various electronic devices that utilize semiconductor packages, such as smartphones, tablets, and computers.
• It can be used in automotive electronics, aerospace systems, and industrial equipment that require reliable and compact semiconductor packaging.

Problems Solved

• The underfill material and conductive layer address the challenge of maintaining structural integrity and electrical connectivity in a semiconductor package.
• The encapsulating material provides protection against environmental factors, such as moisture and temperature variations.

Benefits

• The interconnect structure and underfill material enhance the mechanical stability of the semiconductor package, reducing the risk of damage during handling and operation.
• The conductive layer improves electrical performance by ensuring efficient signal transmission between the dies.
• The encapsulating material offers protection against external factors, increasing the lifespan and reliability of the semiconductor package.

Abstract

A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.

PROTECTION LAYER FOR SEMICONDUCTOR DEVICE (18186754)

Main Inventor

I-Han Huang

Brief explanation

The present disclosure describes a method for forming a semiconductor structure with an oxide structure on a wafer edge. This method involves several steps, including:

• Forming a device layer on a first substrate
• Forming an interconnect layer on the device layer
• Forming an oxide structure on the top surface and sidewall surface of the interconnect layer
• Forming a bonding layer on the oxide structure and interconnect layer
• Bonding the device layer to a second substrate using the bonding layer

Potential applications of this technology include:

• Semiconductor manufacturing
• Integrated circuit fabrication
• Wafer bonding processes

The problems solved by this technology include:

• Ensuring a strong and reliable bond between the device layer and the second substrate
• Providing protection to the interconnect layer and preventing damage during the bonding process
• Facilitating the integration of different semiconductor structures

The benefits of this technology include:

• Improved structural integrity and reliability of the semiconductor structure
• Enhanced protection for the interconnect layer
• Increased flexibility in semiconductor manufacturing processes

Abstract

The present disclosure describes a method to form a semiconductor structure having an oxide structure on a wafer edge. The method includes forming a device layer on a first substrate, forming an interconnect layer on the device layer, forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer, forming a bonding layer on the oxide structure and the interconnect layer, and bonding the device layer to a second substrate with the bonding layer.

Wafer Level Multi-Die Structure Formation (17839946)

Main Inventor

Shan-Yu Huang

Brief explanation

The patent application describes a method for arranging an array of dies on a substrate, where each die contains multiple functional transistors. The dies are surrounded by first seal rings, which define corner regions between subsets of the dies. Within these corner regions, various structures such as test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks are placed. Electrical interconnection elements are used to connect adjacent dies in the array. The entire array, including the dies, seal rings, structures, and interconnection elements, is then surrounded by a second seal ring.

• An array of dies is formed on a substrate, with each die containing multiple functional transistors.
• First seal rings are placed around each die, creating corner regions between subsets of the dies.
• Structures such as test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks are placed within the corner regions.
• Electrical interconnection elements are used to connect adjacent dies in the array.
• A second seal ring surrounds the entire array, including the dies, seal rings, structures, and interconnection elements.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Electronics industry

Problems Solved

• Efficient arrangement of dies on a substrate
• Electrical interconnection between adjacent dies
• Integration of various structures within the corner regions

Benefits

• Improved functionality and performance of integrated circuits
• Enhanced manufacturing efficiency and yield
• Better alignment and overlay accuracy in semiconductor processes

Abstract

An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING (17806311)

Main Inventor

Chien LI

Brief explanation

The patent application describes a semiconductor package that includes an integrated circuit die mounted to an interposer using connection structures. The package also includes an underfill material between the die and the interposer, which includes shaped fillets that are below the bottom surface of the die. These shaped fillets help reduce the likelihood of stresses and strains that could damage the mold compound from transferring to the mold compound from the underfill material, die, and interposer. This improves the quality and reliability of the semiconductor package, potentially increasing the yield and decreasing the cost.

• Semiconductor package includes an integrated circuit die mounted to an interposer using connection structures.
• Underfill material between the die and the interposer includes shaped fillets below the bottom surface of the die.
• Shaped fillets reduce the likelihood of stresses and strains damaging the mold compound.
• Improved quality and reliability of the semiconductor package.
• Potential increase in yield and decrease in cost of the semiconductor package.

Potential Applications

• Semiconductor manufacturing industry
• Electronics industry
• Integrated circuit packaging industry

Problems Solved

• Reduces the likelihood of stresses and strains damaging the mold compound.
• Improves the quality and reliability of the semiconductor package.

Benefits

• Increased yield of the semiconductor package.
• Decreased cost of the semiconductor package.

Abstract

Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.

HETEROGENOUS BONDING LAYERS FOR DIRECT SEMICONDUCTOR BONDING (18447528)

Main Inventor

Kuang-Wei CHENG

Brief explanation

The abstract describes a method for directly bonding two semiconductor devices using heterogeneous bonding layers. The first bonding layer has a higher concentration of hydroxy-containing silicon, while the second bonding layer has a higher concentration of nitrogen. An anneal process is performed to cause a dehydration reaction, resulting in the formation of silicon oxide bonds between the two bonding layers. The presence of nitrogen in the second bonding layer enhances the effectiveness and strength of the bond.

• A first semiconductor device and a second semiconductor device are bonded together using heterogeneous bonding layers.
• The first bonding layer has a higher concentration of hydroxy-containing silicon.
• The second bonding layer has a higher concentration of nitrogen.
• An anneal process is performed to cause a dehydration reaction.
• The dehydration reaction decomposes the hydroxy components of the first bonding layer.
• Silicon oxide bonds are formed between the first and second bonding layers.
• The presence of nitrogen in the second bonding layer enhances the effectiveness of the dehydration reaction.
• The nitrogen also improves the effectiveness and strength of the bond between the two bonding layers.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication
• Microelectronics industry

Problems Solved

• Enables direct bonding of semiconductor devices
• Improves the strength and effectiveness of the bond between the bonding layers

Benefits

• Enhanced bonding strength
• Improved effectiveness of the dehydration reaction
• Enables the formation of silicon oxide bonds between the bonding layers

Abstract

A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

METHOD OF FORMING PACKAGE STRUCTURE (17838292)

Main Inventor

Wen-Chih Chiou

Brief explanation

The abstract describes a method for bonding a device die to a wafer and forming packages. Here are the key points:

• The method involves attaching a wafer to a wafer chuck with a curved surface.
• A device die is placed on the wafer, with its first dielectric layer in contact with the wafer's second dielectric layer.
• An annealing process is performed to bond the first and second dielectric layers together.
• The device die is then encapsulated with a material.
• Redistribution lines are formed, overlapping the encapsulating material and the device die.
• The encapsulating material is sawed to create multiple packages.

Potential applications of this technology:

• Semiconductor manufacturing
• Electronics packaging industry

Problems solved by this technology:

• Provides a method for bonding device dies to wafers effectively.
• Enables the formation of multiple packages from a single wafer.

Benefits of this technology:

• Improved bonding between dielectric layers, ensuring better performance and reliability.
• Efficient use of wafers, reducing manufacturing costs.
• Simplified packaging process, enabling mass production.

Abstract

A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.

Methods of Forming Packages and Resulting Structures (18151758)

Main Inventor

Chien-Fu Tseng

Brief explanation

Manufacturing flexibility and efficiency are achieved through a method and resulting structure that allows for the formation and alignment of RDL contact features to through silicon vias (TSV's), regardless of any differences in critical dimensions (CD's) between the manufacturing processes for the TSV's and the contact features.

• The method enables the self-aligned exposure of the underlying TSV's without the need for additional photolithography steps.
• The innovation allows for the formation and alignment of RDL contact features to TSV's, even if there are variations in critical dimensions between the two manufacturing processes.
• The method provides manufacturing flexibility by allowing for the use of different processes for forming TSV's and contact features.
• The resulting structure ensures efficient manufacturing by eliminating the need for additional photolithography steps.

Potential Applications

This technology can be applied in various industries and fields, including:

• Semiconductor manufacturing
• Electronics manufacturing
• Microchip fabrication
• Integrated circuit production

Problems Solved

The technology addresses the following problems:

• Mismatch in critical dimensions between the manufacturing processes for TSV's and contact features
• Inefficiency in manufacturing due to the need for additional photolithography steps
• Lack of flexibility in choosing different processes for forming TSV's and contact features

Benefits

The technology offers several benefits, including:

• Improved manufacturing flexibility by allowing the use of different processes for TSV's and contact features
• Enhanced manufacturing efficiency by eliminating the need for additional photolithography steps
• Cost savings by reducing the complexity of the manufacturing process
• Increased reliability and performance of the resulting structure

Abstract

Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.

INTEGRATED STANDARD CELL STRUCTURE (17837925)

Main Inventor

Shih-Hsien Huang

Brief explanation

The abstract describes an integrated circuit (IC) structure that includes a fin structure protruding from a semiconductor substrate. The fin structure has three portions with different widths and extends in a specific direction. The IC structure also includes standard cells with metal gate stacks engaged with different portions of the fin structure, and a filler cell that connects the standard cells.

• The IC structure includes a fin structure with different width portions and a continuous third portion.
• Standard cells with metal gate stacks are engaged with different portions of the fin structure.
• A filler cell is present between the standard cells and includes the continuous third portion of the fin structure.
• The filler cell is defined by a dielectric gate and a third metal gate stack with a one-pitch spacing.

Potential Applications

• This IC structure can be used in various electronic devices such as smartphones, computers, and IoT devices.
• It can be applied in the manufacturing of high-performance processors and memory chips.

Problems Solved

• The integrated circuit structure solves the problem of efficiently utilizing space on a semiconductor substrate.
• It addresses the challenge of connecting standard cells with different widths of the fin structure.

Benefits

• The IC structure allows for compact and efficient integration of standard cells with different widths.
• It enables improved performance and functionality of electronic devices.
• The design provides better utilization of space on a semiconductor substrate.

Abstract

An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion. The IC further includes a dielectric gate defining a first boundary of the filler cell and a third metal gate stack defining a second boundary of the filler cell, where the dielectric gate and the third metal gate stack are separated by a one-pitch spacing.

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING SAME (18447857)

Main Inventor

Liu HAN

Brief explanation

The abstract describes a semiconductor device that consists of a cell region with two sets of blocks - a first set with clock gates and a second set with decoupling capacitors. The first set has two or more blocks and the second set has two or more blocks. The first blocks are interleaved with the second blocks.

• The semiconductor device has a cell region with two sets of blocks.
• The first set of blocks includes clock gates.
• The second set of blocks includes decoupling capacitors.
• There are two or more blocks in each set.
• The first blocks are interleaved with the second blocks.

Potential Applications

• Integrated circuits
• Electronic devices
• Semiconductor manufacturing

Problems Solved

• Efficient power management in semiconductor devices
• Reduction of noise and interference in electronic circuits
• Improved performance and reliability of integrated circuits

Benefits

• Enhanced power control and management
• Reduced noise and interference in electronic circuits
• Improved performance and reliability of semiconductor devices

Abstract

A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

INTEGRATED CIRCUIT LAYOUT METHOD (18448155)

Main Inventor

Po-Zeng KANG

Brief explanation

The abstract describes a method for generating an IC layout diagram, which involves positioning a resistor unit cell and a MOS unit cell in the diagram, overlapping them with via regions, and storing the diagram in a storage device.

• The method involves positioning a resistor unit cell and a MOS unit cell in an IC layout diagram.
• The resistor unit cell includes a resistor with a source/drain metal region.
• The resistor unit cell is overlapped with a first via region.
• The MOS unit cell is overlapped with a second via region.
• The first and second via regions are overlapped with a continuous conductive region.
• The resulting IC layout diagram is stored in a storage device.

Potential applications of this technology:

• Integrated circuit design and layout
• Semiconductor manufacturing

Problems solved by this technology:

• Efficient and accurate generation of IC layout diagrams
• Simplified placement and overlapping of different unit cells

Benefits of this technology:

• Improved productivity in IC design
• Enhanced accuracy in IC layout diagrams
• Streamlined manufacturing processes

Abstract

A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18097255)

Main Inventor

Ya-Yi TSAI

Brief explanation

The patent application describes a semiconductor device structure and methods for its formation. The structure includes a fin placed on a semiconductor substrate, with the fin having a certain width. An isolation region surrounds the fin, and a gate electrode is positioned over both the fin and the isolation region. The gate electrode is filled with a material that comes into contact with a flat portion of the semiconductor substrate's top surface, which has a width greater than that of the fin.

• The structure includes a fin placed on a semiconductor substrate
• An isolation region surrounds the fin
• A gate electrode is positioned over the fin and the isolation region
• The gate electrode is filled with a material
• The fill material comes into contact with a flat portion of the semiconductor substrate's top surface
• The flat portion of the top surface has a width greater than that of the fin

Potential Applications

This technology has potential applications in the field of semiconductor devices, particularly in the development of more efficient and high-performance devices.

Problems Solved

The patent application addresses the need for improved semiconductor device structures that can enhance performance and efficiency. By utilizing a fin structure and a fill material in the gate electrode, the technology aims to overcome limitations of conventional designs.

Benefits

The described semiconductor device structure offers several benefits:

• Improved performance and efficiency
• Enhanced functionality of semiconductor devices
• Potential for smaller device sizes and increased integration
• Better control over electrical properties of the device structure.

Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a fin disposed over a semiconductor substrate, and the fin has a first width. The structure further includes an isolation region disposed around the fin, a gate electrode disposed over the fin and the isolation region, and a fill material disposed in the gate electrode. The fill material is in contact with a top surface of a portion of the semiconductor substrate, the top surface has at least a portion having a substantially flat cross-section, and the portion of the top surface has a second width substantially greater than the first width.

INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME (18448101)

Main Inventor

Te-Hsin CHIU

Brief explanation

The abstract describes an integrated circuit that includes three flip-flops on a substrate, with power rails on the back-side of the substrate. The flip-flops are arranged in a linear manner, with each flip-flop abutting the next one at a boundary. The conductive structures of each flip-flop extend in the same direction.

• The integrated circuit includes three flip-flops on a substrate.
• Power rails are located on the back-side of the substrate.
• The flip-flops are arranged in a linear manner.
• Each flip-flop abuts the next one at a boundary.
• The conductive structures of each flip-flop extend in the same direction.
• The flip-flops are located on the front-side of the substrate.

Potential Applications

• This integrated circuit design can be used in various electronic devices and systems that require multiple flip-flops.
• It can be applied in digital logic circuits, microprocessors, memory units, and other complex electronic systems.

Problems Solved

• The integration of multiple flip-flops on a substrate allows for more efficient and compact circuit designs.
• The linear arrangement of the flip-flops simplifies the routing of signals and reduces the complexity of interconnections.

Benefits

• The use of power rails on the back-side of the substrate helps in efficient power distribution and reduces signal interference.
• The linear arrangement of the flip-flops allows for easier signal routing and reduces the overall complexity of the circuit design.
• The integration of multiple flip-flops on a single substrate increases the overall functionality and performance of the integrated circuit.

Abstract

An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.

IMAGE SENSOR (17837534)

Main Inventor

Chun-Hao CHUANG

Brief explanation

The present disclosure describes a three-chip complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the image sensor. The image sensor consists of three chips bonded together to form a complete system.

• The first chip includes image sensing elements, transfer transistors, and diffusion wells. These components are responsible for capturing and transferring the image data.
• The first chip also includes a shared ground node and deep trench isolation (DTI) structures. The shared ground node helps in maintaining a common reference point for all the image sensing elements, while the DTI structures provide isolation between adjacent image sensing elements.
• The second chip is bonded to the first chip and includes a source follower, a reset transistor, a row select transistor, and an in-pixel circuit. The source follower is connected to the diffusion wells and helps in amplifying the signal from the image sensing elements. The reset transistor and row select transistor control the readout process, and the in-pixel circuit performs additional processing on the image data.
• The third chip is bonded to the second chip and includes an application-specific circuit. This circuit is connected to the in-pixel circuit and can be customized for specific applications or functionalities.

Potential applications of this technology:

• Digital cameras and camcorders: The three-chip image sensor can be used in consumer electronic devices for capturing high-quality images and videos.
• Medical imaging: The image sensor can be utilized in medical devices such as endoscopes or ultrasound machines to capture detailed images for diagnostic purposes.
• Surveillance systems: The three-chip image sensor can be integrated into security cameras to provide enhanced image quality and advanced features like object recognition.

Problems solved by this technology:

• Improved image quality: The three-chip image sensor design allows for better control over the image capture process, resulting in higher resolution and reduced noise.
• Enhanced functionality: The inclusion of an application-specific circuit enables the image sensor to be customized for specific applications, providing additional features and capabilities.
• Efficient signal processing: The in-pixel circuit performs processing on the image data within each pixel, reducing the need for external processing and improving overall system efficiency.

Benefits of this technology:

• Higher image quality: The three-chip image sensor design, along with the inclusion of DTI structures, helps in reducing crosstalk between adjacent image sensing elements, resulting in sharper and more accurate images.
• Customizability: The presence of an application-specific circuit allows for the image sensor to be tailored to specific applications, providing flexibility and versatility.
• Improved efficiency: The in-pixel circuitry reduces the need for external processing, leading to faster image capture and reduced power consumption.

Abstract

The present disclosure describes a three-chip complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the image sensor. The image sensor a first chip including a plurality of image sensing elements, transfer transistors and diffusion wells corresponding to the plurality of image sensing elements, a ground node shared by the plurality of image sensing elements, and deep trench isolation (DTI) structures extending from the shared ground node and between adjacent image sensing elements of the plurality of image sensing elements. The image sensor further includes a second chip bonded to the first chip and including a source follower, a reset transistor, a row select transistor, and an in-pixel circuit, where the source follower is electrically coupled to the diffusion wells. The image sensor further includes a third chip bonded to the second chip and including an application-specific circuit, where the application-specific circuit is electrically coupled to the in-pixel circuit.

APPARATUS AND METHODS FOR SENSING LONG WAVELENGTH LIGHT (18232323)

Main Inventor

Yun-Wei CHENG

Brief explanation

The patent application describes apparatus and methods for sensing long wavelength light using a semiconductor device.

• The semiconductor device includes a carrier, a device layer, a semiconductor layer, and an insulation layer.
• The semiconductor layer consists of isolation regions and pixel regions.
• The isolation regions are made of a first semiconductor material.
• The pixel regions are made of a second semiconductor material that is different from the first semiconductor material.

Potential Applications

• Long wavelength light sensing in various industries such as telecommunications, medical imaging, and environmental monitoring.
• Integration into cameras, sensors, and other devices that require detection of long wavelength light.

Problems Solved

• Enables efficient sensing of long wavelength light by utilizing different semiconductor materials in the pixel regions.
• Provides isolation regions to prevent interference and improve the accuracy of light sensing.

Benefits

• Improved sensitivity and accuracy in detecting long wavelength light.
• Enhanced performance and reliability of devices incorporating this technology.
• Potential for miniaturization and integration into various applications.

Abstract

Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.

PIXEL SENSOR INCLUDING REFRACTION STRUCTURES (18366175)

Main Inventor

Wei-Lin CHEN

Brief explanation

The abstract describes a pixel sensor that includes a main deep trench isolation (DTI) structure and one or more sub-DTI structures in the substrate. This design aims to increase the quantum efficiency of the pixel sensor at large incident angles. The sub-DTI structures are located within the perimeter of the main DTI structure and above a photodiode. They are filled with an oxide material to increase light penetration and reduce reflections at the top surface of the substrate. This allows incident light to refract into the substrate and towards the photodiode.

• Pixel sensor with main DTI structure and sub-DTI structures in the substrate
• Sub-DTI structures located within the perimeter of the main DTI structure and above the photodiode
• Sub-DTI structures filled with oxide material to increase light penetration
• Reduces reflections at the top surface of the substrate
• Allows incident light to refract into the substrate and towards the photodiode

Potential Applications

• Digital cameras
• Smartphone cameras
• Surveillance cameras
• Medical imaging devices
• Scientific imaging devices

Problems Solved

• Increase quantum efficiency of pixel sensors at large incident angles
• Reduce reflections and improve light penetration into the photodiode

Benefits

• Improved image quality in low-light conditions
• Enhanced sensitivity to light at large incident angles
• Reduced noise and improved signal-to-noise ratio
• Increased overall performance of pixel sensors

Abstract

A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles. The one or more sub-DTI structures may be located within the perimeter of the main DTI structure and above a photodiode. The one or more sub-DTI structures may be configured to provide a path of travel for incident light into the photodiode from large incident angles in that the one or more sub-DTI structures may be filled with an oxide material to increase light penetration into the one or more sub-DTI structures. This may reduce reflections at a top surface of the substrate, thereby permitting incident light to refract into the substrate and toward the photodiode.

METHOD OF MANUFACTURING SEMICONDUCTOR IMAGE SENSOR (18448093)

Main Inventor

Li-Wen HUANG

Brief explanation

The patent application describes a method of manufacturing a semiconductor device with two types of light sensing units arranged on a substrate. The first type of units receives less radiation than the second type. Some of the second type units are placed adjacent to the first type units. Isolation structures are used to separate the different types of units and a reflective layer is placed above the first type units.

• The method involves placing two types of light sensing units on a substrate.
• The first type of units receives less radiation than the second type.
• Some of the second type units are placed next to the first type units.
• Isolation structures are used to separate the different types of units.
• A reflective layer is placed above the first type units.

Potential Applications

This technology has potential applications in various fields, including:

• Image sensors for digital cameras and smartphones.
• Optical communication devices.
• Medical imaging devices.
• Industrial automation and robotics.

Problems Solved

The technology addresses several problems in the manufacturing of semiconductor devices, such as:

• Efficiently detecting different levels of radiation.
• Minimizing interference between adjacent light sensing units.
• Improving the overall sensitivity and performance of the device.
• Enhancing the accuracy and quality of image and data capture.

Benefits

The use of this technology offers several benefits, including:

• Improved sensitivity and accuracy in detecting different levels of radiation.
• Enhanced performance and efficiency of the semiconductor device.
• Reduction in interference between adjacent light sensing units.
• Higher quality and resolution in image and data capture.
• Increased versatility and applicability in various industries.

Abstract

A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate. Each of the first type of light sensing units is operable to receive less radiation than each of the second type of light sensing units. At least one of the second type of light sensing units is adjacent to a portion of at least one of the first type of light sensing units. The method includes disposing a first isolation structure between one of the first type of light sensing units and one of the second type of light sensing units; and disposing a second isolation structure between the adjacent first type of light sensing units. The method includes disposing a reflective layer above the first type of light sensing units.

INTEGRATION OF SOLAR CELL AND IMAGE SENSOR (17892846)

Main Inventor

Feng-Chien Hsieh

Brief explanation

The abstract describes an integrated circuit structure that combines a solar cell and an image sensor array. The structure includes multiple photodiodes on a substrate, an interconnect structure, bonding layers, a second substrate, and a transparent conductive oxide layer.

• The integrated circuit structure combines a solar cell and an image sensor array.
• The structure includes a substrate with multiple photodiodes.
• An interconnect structure is placed on the substrate.
• Bonding layers are added on top of the interconnect structure.
• A second substrate is placed on the bonding layers.
• A transparent conductive oxide layer is applied on the second substrate.

Potential applications of this technology:

• Solar-powered image sensors for various devices and systems.
• Integration of solar energy harvesting and image sensing capabilities in a single chip.
• Efficient power generation and image capturing in portable devices like smartphones and cameras.

Problems solved by this technology:

• Separate solar cells and image sensor arrays require more space and complex integration.
• Combining both functionalities in a single chip reduces the overall size and complexity of the system.
• Enables more compact and efficient devices with integrated solar power and image sensing capabilities.

Benefits of this technology:

• Space-saving integration of solar cells and image sensors.
• Simplified manufacturing process with fewer components.
• Enhanced energy efficiency and performance in portable devices.
• Enables the development of smaller and more versatile devices with integrated solar power and image sensing capabilities.

Abstract

The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array. An integrated structure according to the present disclosure includes a first substrate including a plurality of photodiodes, an interconnect structure disposed on the first substrate, a first bonding layer disposed on the interconnect structure, a second bonding layer disposed on the first bonding layer, a second substrate disposed on the second bonding layer, and a transparent conductive oxide layer disposed on the second substrate.

REDUCED CROSS-TALK IN COLOR AND INFRARED IMAGE SENSOR (18366776)

Main Inventor

Keng-Yu Chou

Brief explanation

The patent application describes an image sensor device that includes two image sensor elements within a substrate. The device also includes an interconnect structure with conductive wires, conductive vias, and an absorption structure.

• The first image sensor element generates electrical signals from electromagnetic radiation in a specific range of wavelengths.
• The second image sensor element generates electrical signals from electromagnetic radiation in a different range of wavelengths.
• The second image sensor element is positioned next to the first image sensor element.
• The first image sensor element is located above the absorption structure and is spaced between the sidewalls of the absorption structure.

Potential applications of this technology:

• Digital cameras
• Smartphone cameras
• Surveillance cameras
• Medical imaging devices

Problems solved by this technology:

• Allows for capturing images in different ranges of wavelengths simultaneously.
• Provides a compact design by integrating multiple image sensor elements within a single device.

Benefits of this technology:

• Improved image quality by capturing a wider range of wavelengths.
• Compact and efficient design for image sensor devices.
• Enables the development of multi-spectral imaging applications.

Abstract

Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.

IMAGE SENSOR WITH HIGH QUANTUM EFFICIENCY (18447890)

Main Inventor

Feng-Chien HSIEH

Brief explanation

The present disclosure describes an image sensor device and a method for forming the same. The device includes a semiconductor layer with a first and second surface. It also includes an interconnect structure formed over the first surface, radiation sensing regions formed in the second surface, a metal stack over the second radiation sensing region, and a passivation layer over the first radiation sensing region.

• The image sensor device includes a semiconductor layer with two surfaces.
• An interconnect structure is formed over the first surface of the semiconductor layer.
• Radiation sensing regions are formed in the second surface of the semiconductor layer.
• A metal stack is formed over the second radiation sensing region.
• A passivation layer is formed through the metal stack and over the top surface of the first radiation sensing region.
• The metal stack is located between the passivation layer and the other top surface of the second radiation sensing region.

Potential Applications

• Image sensors for digital cameras, smartphones, and other electronic devices.
• Medical imaging devices.
• Surveillance cameras and security systems.
• Automotive cameras for advanced driver assistance systems (ADAS).

Problems Solved

• Provides a structure for an image sensor device with improved radiation sensing capabilities.
• Enables efficient interconnectivity and integration of components in the image sensor device.
• Protects the radiation sensing regions from external factors and enhances their performance.

Benefits

• Enhanced image quality and sensitivity in image sensor devices.
• Improved reliability and durability of the image sensor device.
• Enables miniaturization and integration of image sensor devices in various electronic devices.
• Cost-effective manufacturing process for image sensor devices.

Abstract

The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.

DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF (17838994)

Main Inventor

Bi-Shen LEE

Brief explanation

The patent application describes a Deep Trench Isolation (DTI) structure with a composite passivation layer. The composite passivation layer includes a hole accumulation layer and a defect repairing layer, which reduces lattice defects and the density of interface trap (DIT) at the interface. The hole accumulation layer is enhanced by an oxidization treatment.

• The DTI structure includes a composite passivation layer with a hole accumulation layer and a defect repairing layer.
• The defect repairing layer reduces lattice defects and the density of interface trap at the interface.
• The hole accumulation layer is enhanced by an oxidization treatment.
• The composite passivation layer improves the flat band voltage of the DTI structure.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuit fabrication
• Electronics industry

Problems solved by this technology:

• Reduces lattice defects and density of interface trap at the interface
• Improves the flat band voltage of the DTI structure

Benefits of this technology:

• Strong hole accumulation
• Increased performance and reliability of semiconductor devices

Abstract

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

VERTICALLY ARRANGED SEMICONDUCTOR PIXEL SENSOR (18447529)

Main Inventor

Feng-Chien HSIEH

Brief explanation

The abstract describes a pixel sensor design that improves performance and reduces size by vertically arranging the photodiode and floating diffusion regions. This arrangement allows the photodiode to collect more photons in a given area, increasing the sensor's performance. The transfer gate surrounding these regions provides better control over the transfer of photocurrent and reduces switching delay.

• The pixel sensor includes a vertically stacked photodiode and floating diffusion region.
• Vertical arrangement increases the area for photon collection, improving sensor performance.
• The transfer gate surrounds the regions, providing a larger gate switching area.
• Increased gate switching area allows for better control over photocurrent transfer and reduces switching delay.

Potential Applications

• Digital cameras
• Smartphone cameras
• Surveillance cameras
• Medical imaging devices

Problems Solved

• Limited area for photon collection in pixel sensors
• Inefficient control over photocurrent transfer
• Switching delay in pixel sensors

Benefits

• Improved performance of pixel sensors
• Reduced size of pixel sensors
• Better control over photocurrent transfer
• Reduced switching delay in pixel sensors

Abstract

A pixel sensor may include a vertically arranged (or vertically stacked) photodiode region and floating diffusion region. The vertical arrangement permits the photodiode region to occupy a larger area of a pixel sensor of a given size relative to a horizontal arrangement, which increases the area in which the photodiode region can collect photons. This increases performance of the pixel sensor and permits the overall size of the pixel sensor to be reduced. Moreover, the transfer gate may surround at least a portion of the floating diffusion region and the photodiode region, which provides a larger gate switching area relative to a horizontal arrangement. The increased gate switching area may provide greater control over the transfer of the photocurrent and/or may reduce switching delay for the pixel sensor.

INTEGRATED CIRCUIT WITH FEOL RESISTOR (18448111)

Main Inventor

Tien-Chien HUANG

Brief explanation

The patent application describes a method for forming a semiconductor device with a metal gate structure and a metal resistor structure. Here are the key points:

• The method involves creating a shallow trench isolation (STI) region in a semiconductor substrate to separate an active region and a passive region.
• Sacrificial gate structures are formed over the active and passive regions.
• Source/drain regions are formed in both the active and passive regions.
• The sacrificial gate structures are then replaced with a metal gate structure and a metal resistor structure.
• A gate contact is formed over the metal gate structure, and resistor contacts are formed over the metal resistor structure.
• The metal resistor structure, acting as a dummy gate, is electrically connected to a set of metal lines through the resistor contacts.

Potential applications of this technology:

• Semiconductor devices with improved performance and functionality.
• Integrated circuits with metal gate structures and metal resistor structures.
• Devices requiring precise control of electrical resistance.

Problems solved by this technology:

• Provides a method for forming metal gate structures and metal resistor structures in a semiconductor device.
• Enables the integration of metal lines with the metal resistor structure, allowing for efficient electrical coupling.

Benefits of this technology:

• Enhanced device performance and functionality.
• Improved control over electrical resistance.
• Increased integration capabilities for semiconductor devices.

Abstract

A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (17827779)

Main Inventor

Yi-Ruei Jhan

Brief explanation

The abstract describes a semiconductor device and a method of forming it. The device includes a substrate with multiple fins, semiconductor nanosheets stacked on the fins, gate stacks wrapping the nanosheets, an isolation structure around the fins, and a separator structure on the isolation structure to separate the gate stacks.

• The device includes a substrate with multiple fins.
• Semiconductor nanosheets are stacked on the fins.
• Gate stacks wrap the semiconductor nanosheets.
• An isolation structure surrounds the fins.
• A separator structure is placed on the isolation structure to separate the gate stacks.
• The separator structure consists of a body and a cap.
• The cap has two portions, with the second portion wrapped by the first portion.

Potential applications of this technology:

• Semiconductor devices for various electronic applications.
• High-performance transistors for computing and communication devices.
• Power-efficient and compact integrated circuits.

Problems solved by this technology:

• Provides a structure for efficient stacking of semiconductor nanosheets.
• Enables effective isolation and separation of gate stacks.
• Enhances the performance and functionality of semiconductor devices.

Benefits of this technology:

• Improved performance and efficiency of semiconductor devices.
• Enables the development of smaller and more compact electronic devices.
• Enhances the integration and functionality of integrated circuits.

Abstract

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a semiconductor device. The semiconductor device includes a substrate including a plurality of fins, a plurality of semiconductor nanosheets stacked on the plurality of fins, a plurality of gate stacks wrapping the plurality of semiconductor nanosheets, an isolation structure around the plurality of fins, and a separator structure on the isolation structure to separate the plurality of gate stacks from each other. The separator structure includes a body and a cap on the body. The cap includes a first portion and a second portion. Sidewalls and bottom of the second portion is wrapped by the first portion.

Epitaxial Structures In Semiconductor Devices (18128061)

Main Inventor

Cheng-Wei CHANG

Brief explanation

The abstract describes a semiconductor device and a method of fabricating it. The device includes a substrate, a fin base, nanostructured channel regions, a gate structure, a source/drain region, an air spacer, and a dielectric layer.

• The semiconductor device is made up of multiple components that work together to perform various functions.
• The fin base is a part of the device that is placed on the substrate.
• The nanostructured channel regions are stacked on a portion of the fin base and play a crucial role in the device's operation.
• The gate structure surrounds the nanostructured channel regions and helps control the flow of current.
• The source/drain region is located on another portion of the fin base and is responsible for providing input/output connections.
• An air spacer is placed between the source/drain region and the fin base, providing insulation and preventing interference.
• A dielectric layer is placed between the air spacer and the fin base, further enhancing insulation and protection.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices, such as smartphones, computers, and tablets.
• It can also be used in advanced computing systems, data centers, and high-performance computing applications.

Problems solved by this technology:

• The nanostructured channel regions and the gate structure help improve the performance and efficiency of the semiconductor device.
• The air spacer and dielectric layer provide insulation and protection, reducing interference and enhancing the device's reliability.

Benefits of this technology:

• The semiconductor device offers improved performance and efficiency compared to traditional devices.
• It provides better insulation and protection, resulting in enhanced reliability and durability.
• The device can be used in a wide range of electronic applications, making it versatile and adaptable.

Abstract

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, a stack of nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, an air spacer disposed between the S/D region and the fin base, and a dielectric layer disposed between the air spacer and the fin base.

Transistor Gate Structures and Methods of Forming the Same (18150474)

Main Inventor

Chung-Wei Hsu

Brief explanation

The patent application describes a device with nanostructures and gate spacers on a substrate, along with a dielectric wall between them. The gate structure surrounds the nanostructures and fills the areas between the dielectric wall and the nanostructures.

• The device includes an isolation region on a substrate.
• There are first and second nanostructures above the isolation region.
• First and second gate spacers are present on the respective nanostructures.
• A dielectric wall separates the gate spacers along one direction and the nanostructures along another direction.
• The gate structure surrounds the nanostructures and fills the areas between the dielectric wall and the nanostructures.

Potential Applications

• This technology can be used in the development of advanced electronic devices.
• It may find applications in the field of nanoelectronics and semiconductor industry.

Problems Solved

• The device provides improved isolation between the nanostructures and gate spacers.
• It allows for better control and manipulation of the electrical properties of the nanostructures.

Benefits

• The device offers enhanced performance and functionality in electronic devices.
• It enables more efficient use of space and resources in the fabrication process.
• The technology may lead to the development of smaller and more powerful electronic devices.

Abstract

In an embodiment, a device includes: an isolation region on a substrate; first nanostructures above the isolation region; second nanostructures above the isolation region; a first gate spacer on the first nanostructures; a second gate spacer on the second nanostructures; a dielectric wall between the first gate spacer and the second gate spacer along a first direction in a top-down view, the dielectric wall disposed between the first nanostructures and the second nanostructures along a second direction in the top-down view, the first direction perpendicular to the second direction; and a gate structure around the first nanostructures and around the second nanostructures, a first portion of the gate structure filling a first area between the dielectric wall and the first nanostructures, a second portion of the gate structure filling a second area between the dielectric wall and the second nanostructures.

SEMICONDUCTOR DEVICE WITH DIELECTRIC LINERS ON GATE REFILL METAL (17837613)

Main Inventor

Yuan-Hsiang WU

Brief explanation

The patent application describes a device that includes various components such as a gate structure, gate spacers, source/drain regions, a refill metal structure, and a dielectric liner. These components are arranged in a specific configuration to improve the performance and functionality of the device.

• The device includes a gate structure placed on a substrate.
• Two gate spacers are positioned on opposite sides of the gate structure.
• Source/drain regions are located at a distance from the gate structure, partially separated by the gate spacers.
• A refill metal structure is present on the gate structure, positioned between the two gate spacers.
• A dielectric liner is placed on top of the gate structure, serving as a barrier between the refill metal structure and the first gate spacer.

Potential applications of this technology:

• This device configuration can be used in various electronic devices such as transistors, integrated circuits, and microprocessors.
• It can enhance the performance and efficiency of these electronic devices, leading to improved functionality and faster processing speeds.

Problems solved by this technology:

• The specific arrangement of the gate structure, gate spacers, and refill metal structure helps to reduce leakage current and improve the overall performance of the device.
• It addresses issues related to the proximity of the source/drain regions to the gate structure, ensuring proper separation and minimizing interference.

Benefits of this technology:

• The device configuration described in the patent application can lead to improved performance, efficiency, and functionality of electronic devices.
• It can help in achieving faster processing speeds and reducing power consumption.
• The reduction in leakage current can enhance the reliability and lifespan of the device.

Abstract

A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17837833)

Main Inventor

Tzu-Ging LIN

Brief explanation

The patent application describes a semiconductor device structure and methods of forming it. The structure includes a substrate and an isolation structure between two neighboring transistors. The isolation structure consists of a dielectric feature and an insulating material below it. The insulating material has an upper portion with a first sidewall and a top surface in contact with the dielectric feature, a bottom portion with a second sidewall in contact with the substrate, and a middle portion with a third sidewall between the first and second sidewalls. The structure also includes a dielectric material in contact with the dielectric feature, first sidewall, third sidewall, and substrate.

• The patent application describes a new semiconductor device structure.
• The structure includes an isolation structure between neighboring transistors.
• The isolation structure consists of a dielectric feature and an insulating material.
• The insulating material has an upper portion, a bottom portion, and a middle portion.
• The upper portion has a first sidewall and a top surface in contact with the dielectric feature.
• The bottom portion has a second sidewall in contact with the substrate.
• The middle portion has a third sidewall between the first and second sidewalls.
• The structure also includes a dielectric material in contact with various components.

Potential Applications

This technology can be applied in various semiconductor devices, including:

• Integrated circuits
• Microprocessors
• Memory devices
• Power devices
• Sensors

Problems Solved

The described semiconductor device structure solves several problems in the field, such as:

• Improving isolation between neighboring transistors
• Enhancing the performance and reliability of semiconductor devices
• Reducing leakage current and parasitic capacitance
• Increasing integration density and packing more transistors in a smaller area

Benefits

The use of this semiconductor device structure offers several benefits, including:

• Improved electrical isolation between transistors
• Enhanced performance and reliability of semiconductor devices
• Reduced leakage current and parasitic capacitance, leading to lower power consumption
• Increased integration density, allowing for more functionality in a smaller footprint

Abstract

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate and an isolation structure disposed on the substrate and between two neighboring transistors. The isolation structure includes a dielectric feature, an insulating material disposed below the dielectric feature. The insulating material includes an upper portion comprising a first sidewall and a top surface in contact with the dielectric feature, and a bottom portion having a second sidewall, wherein the second sidewall is surrounded by and in contact with the substrate. The insulating material further includes a middle portion having a third sidewall disposed between the first sidewall and the second sidewall. The semiconductor device structure also includes a dielectric material in contact with the dielectric feature, the first sidewall, the third sidewall, and the substrate.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17839127)

Main Inventor

Li-Zhen YU

Brief explanation

The patent application describes a method for forming a semiconductor device structure with a gate structure, source/drain structures, and a trench. The method involves depositing liner layers and a dummy material layer, etching the dummy material layer, and forming a power via structure. The dummy material layer is then removed to create an opening, and a sealing layer is formed over the opening with an air spacer underneath.

• The method involves forming a gate structure, source/drain structures, and a trench.
• Liner layers and a dummy material layer are deposited in the trench.
• The dummy material layer is etched, and a second liner layer is deposited.
• A power via structure is formed in the trench.
• The dummy material layer is removed to create an opening.
• A sealing layer is formed over the opening with an air spacer underneath.

Potential Applications

• This method can be used in the manufacturing of semiconductor devices.
• It can be applied in the production of various electronic components.

Problems Solved

• The method provides a way to form a semiconductor device structure with improved sealing and air spacer features.
• It solves the problem of creating a reliable and efficient power via structure.

Benefits

• The method allows for the formation of a sealing layer with an air spacer, which can enhance the performance and reliability of the semiconductor device.
• It provides a more efficient and effective way to create a power via structure.
• The method can improve the overall functionality and durability of semiconductor devices.

Abstract

A method for forming a semiconductor device structure includes forming a gate structure surrounding the nanostructures. The method also includes forming source/drain structures over opposite sides of the gate structure. The method also includes forming a trench beside the source/drain structures. The method also includes depositing a first liner layer in the trench. The method also includes depositing a dummy material layer over the first liner layer. The method also includes etching the dummy material layer. The method also includes depositing a second liner layer over the dummy material layer. The method also includes forming a power via structure in the trench. The method also includes removing the dummy material layer to form an opening between the first liner layer and the second liner layer. The method also includes forming a sealing layer over the opening. An air spacer is formed under the sealing layer.

MULTI-SILICIDE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME (18447580)

Main Inventor

Chung-Liang CHENG

Brief explanation

The patent application describes a semiconductor device that includes multiple layers of silicide, a contact structure, and a dielectric material. The device also involves a controller that determines etch process parameters for an atomic layer etch (ALE) process.

• The semiconductor device has a multi-silicide structure with at least two conformal silicide layers.
• The multi-silicide structure includes a first layer on a source/drain, a second layer on the first layer, and a capping layer on the second layer.
• The device includes a contact structure on the multi-silicide structure.
• A dielectric material surrounds the contact structure.
• A controller determines etch process parameters for an atomic layer etch (ALE) process on the device.

Potential Applications

• This technology can be applied in the manufacturing of semiconductor devices, such as integrated circuits and microprocessors.
• It can improve the performance and reliability of these devices by enhancing the contact structure and optimizing the etch process.

Problems Solved

• The multi-silicide structure helps to improve the electrical conductivity and contact resistance of the semiconductor device.
• The use of conformal silicide layers and a capping layer enhances the stability and durability of the device.
• The controller's determination of etch process parameters ensures precise and efficient etching during the manufacturing process.

Benefits

• The multi-silicide structure improves the overall performance and functionality of the semiconductor device.
• The optimized etch process parameters result in better control and accuracy during the manufacturing process.
• The enhanced contact structure and stability of the device lead to improved reliability and longevity.

Abstract

A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.

Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same (18177409)

Main Inventor

Szu-Hua Chen

Brief explanation

The patent application describes a method for forming semiconductor structures using a dummy gate stack and gate spacers. The method involves depositing two dielectric layers, etching them back to form gate spacers, and then replacing the dummy gate stack with a gate structure. The dielectric layers have specific properties to enhance the performance of the semiconductor structure.

• The method involves forming a dummy gate stack on a semiconductor fin over a substrate.
• Two dielectric layers are conformally deposited over the substrate.
• The first dielectric layer has a lower dielectric constant than silicon oxide.
• The second dielectric layer is less easily oxidized than the first dielectric layer.
• The first and second dielectric layers are etched back to form gate spacers along the sidewall of the dummy gate stack.
• Source/drain features are formed in and over the semiconductor fin adjacent to the dummy gate stack.
• The dummy gate stack is then replaced with a gate structure.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuit fabrication
• Transistor design and production

Problems solved by this technology:

• Enhances the performance and efficiency of semiconductor structures
• Improves the reliability and stability of gate spacers
• Reduces the risk of oxidation during fabrication

Benefits of this technology:

• Improved transistor performance
• Enhanced integration density
• Increased reliability and stability of semiconductor structures

Abstract

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.

Parasitic Capacitance Reduction (18357307)

Main Inventor

Jia-Heng Wang

Brief explanation

The present disclosure describes semiconductor devices and methods of forming them. Here are the key points:

• The semiconductor device includes a fin-shaped structure that extends over a substrate in one direction.
• An epitaxial feature is formed over the source/drain region of the fin-shaped structure.
• A gate structure is placed over the channel region of the fin-shaped structure, perpendicular to the first direction.
• A source/drain contact is positioned over the epitaxial feature.
• The bottom surface of the gate structure is closer to the substrate than the bottom surface of the source/drain contact.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices, such as smartphones, tablets, and computers.
• It can be utilized in integrated circuits for high-performance computing, data storage, and communication systems.
• The technology can also be applied in automotive electronics, aerospace systems, and medical devices.

Problems solved by this technology:

• The design allows for improved performance and efficiency of the semiconductor device.
• The epitaxial feature over the source/drain region enhances the conductivity and reduces resistance.
• The placement of the gate structure and source/drain contact optimizes the electrical characteristics of the device.

Benefits of this technology:

• The semiconductor device offers enhanced performance and speed due to the optimized design.
• It provides improved conductivity and reduced resistance, leading to more efficient operation.
• The technology enables the development of smaller and more compact electronic devices.

Abstract

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

CASCADED BIPOLAR JUNCTION TRANSISTOR AND METHODS OF FORMING THE SAME (17838894)

Main Inventor

Hong-Shyang WU

Brief explanation

The patent application describes a device and methods for forming the device. The device includes two bipolar junction transistors (BJTs) and an interconnect structure. The BJTs have different regions (base, emitter, and collector) and are placed adjacent to each other on a substrate. The interconnect structure includes conductive lines that connect the regions of the BJTs.

• The device includes two bipolar junction transistors (BJTs) placed adjacent to each other on a substrate.
• The BJTs have different regions - base, emitter, and collector.
• An interconnect structure is formed over the BJTs.
• The interconnect structure includes conductive lines that connect the regions of the BJTs.

Potential Applications

• Integrated circuits
• Electronics manufacturing
• Semiconductor devices

Problems Solved

• Simplifies the formation of a device with multiple BJTs.
• Provides a compact and efficient design for connecting the regions of the BJTs.

Benefits

• Improved performance and functionality of integrated circuits.
• Cost-effective manufacturing process.
• Compact design allows for smaller and more portable electronic devices.

Abstract

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

CHANNEL STRUCTURES INCLUDING DOPED 2D MATERIALS FOR SEMICONDUCTOR DEVICES (18452581)

Main Inventor

Ching-Hua Lee

Brief explanation

The patent application describes a semiconductor device that includes a substrate and a suspended semiconductor structure with a source region, a drain region, and a channel region. The channel region contains a doped two-dimensional material layer on its upper surface. The device also includes an interfacial layer surrounding the channel region and a gate electrode surrounding the interfacial layer.

• The semiconductor device includes a suspended semiconductor structure with a source, drain, and channel region.
• The channel region contains a doped two-dimensional material layer on its upper surface.
• An interfacial layer surrounds the channel region and includes the doped two-dimensional material layer.
• A gate electrode surrounds the interfacial layer.

Potential Applications

• This technology can be used in the development of high-performance transistors.
• It can be applied in the manufacturing of advanced electronic devices such as smartphones, computers, and tablets.
• The semiconductor device can be used in the production of integrated circuits for various applications in the electronics industry.

Problems Solved

• The use of a doped two-dimensional material layer in the channel region improves the performance and efficiency of the semiconductor device.
• The suspended semiconductor structure allows for better control of the electrical properties and reduces interference.
• The interfacial layer helps to enhance the overall performance and stability of the device.

Benefits

• The semiconductor device offers improved performance and efficiency compared to traditional devices.
• It allows for better control of electrical properties and reduces interference.
• The technology enables the production of advanced electronic devices with higher performance and reliability.

Abstract

A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.

FIELD EFFECT TRANSISTOR WITH GATE ISOLATION STRUCTURE AND METHOD (18163857)

Main Inventor

Kuo-Cheng CHIANG

Brief explanation

The patent application describes a device that consists of two vertical stacks of nanostructures formed over a substrate. The device also includes two gate structures and a wall structure between them. Here are the key points:

• The device has a first vertical stack of nanostructures and a second vertical stack adjacent to it.
• The first gate structure is located between the first nanostructures and consists of a first gate portion and a second gate portion.
• The second gate portion extends from one sidewall of the first gate portion to the other sidewall.
• The second sidewall, which is between the first sidewall and the substrate, is made of a different material than the first gate portion.
• There is a second gate structure adjacent to the second nanostructures.
• A wall structure is present between the second gate portion and the second gate structure.

Potential applications of this technology:

• Nanoelectronics: The device could be used in the development of advanced nanoelectronic devices, such as transistors or memory cells.
• Semiconductor industry: The technology could find applications in the semiconductor industry for the fabrication of high-performance integrated circuits.
• Quantum computing: The device's unique structure may have potential applications in the field of quantum computing, where precise control over nanostructures is crucial.

Problems solved by this technology:

• Improved performance: The device's structure allows for better control and manipulation of nanostructures, leading to improved performance in various applications.
• Integration challenges: The technology addresses challenges related to integrating different materials and structures in nanoelectronic devices.
• Miniaturization: The device's design enables the creation of smaller and more efficient electronic components, contributing to the ongoing trend of miniaturization in the industry.

Benefits of this technology:

• Enhanced functionality: The device's unique structure provides enhanced functionality and performance compared to conventional devices.
• Versatility: The technology can be applied to various types of nanostructures and materials, making it versatile for different applications.
• Scalability: The device's design allows for scalability, enabling the production of larger quantities of devices with consistent performance.

Abstract

A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (18360471)

Main Inventor

Sai-Hooi YEONG

Brief explanation

The abstract describes a semiconductor device structure that includes a transistor, a capacitor, and gate spacer layers. The transistor has a source/drain feature adjoining an active region and a gate stack over the active region. The capacitor is positioned above the transistor and consists of a bottom electrode layer on the gate stack and a ferroelectric layer made of a Hf-based dielectric material on the bottom electrode layer. The gate spacer layers surround the gate stack, bottom electrode layer, and ferroelectric layer.

• The semiconductor device structure includes a transistor with a source/drain feature and a gate stack.
• A capacitor is positioned above the transistor, consisting of a bottom electrode layer and a ferroelectric layer made of a Hf-based dielectric material.
• Gate spacer layers surround the gate stack, bottom electrode layer, and ferroelectric layer.

Potential Applications

• This semiconductor device structure can be used in various electronic devices, such as smartphones, tablets, and computers.
• It can be applied in memory devices, logic circuits, and other semiconductor-based technologies.

Problems Solved

• The use of a Hf-based dielectric material in the ferroelectric layer provides improved performance and reliability compared to other materials.
• The gate spacer layers help to protect and isolate the transistor, capacitor, and other components, enhancing the overall functionality and lifespan of the device.

Benefits

• The use of a ferroelectric layer made of a Hf-based dielectric material in the capacitor improves the efficiency and stability of the device.
• The gate spacer layers provide additional protection and isolation, leading to enhanced performance and durability.
• This semiconductor device structure offers potential advancements in memory technology and other semiconductor applications.

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a transistor which includes a source/drain feature adjoining an active region, and a gate stack over the active region. The semiconductor device structure further includes a capacitor above the transistor, the capacitor including a bottom electrode layer on the gate stack and a ferroelectric layer on the bottom electrode layer. The ferroelectric layer is made of a Hf-based dielectric material. The semiconductor device structure further includes gate spacer layers surrounding the gate stack, the bottom electrode layer and the ferroelectric layer.

FIN FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF (17838303)

Main Inventor

Ya-Yi Tsai

Brief explanation

The abstract describes a FinFET, which is a type of transistor used in semiconductor devices. The FinFET includes a semiconductor substrate, a semiconductor fin, a gate structure, and an isolation structure. 

• The semiconductor fin protrudes from the semiconductor substrate.
• The gate structure is placed across a portion of the semiconductor fin.
• The isolation structure interrupts the continuity of another portion of the semiconductor fin.
• The isolation structure consists of two stacked portions, with inclined sidewalls in the first portion and straight sidewalls in the second portion.
• The top surface of the first portion is at the same level as the top surface of the gate structure.

Potential applications of this technology:

• Semiconductor devices such as microprocessors, memory chips, and integrated circuits.
• High-performance computing systems.
• Mobile devices and smartphones.
• Internet of Things (IoT) devices.

Problems solved by this technology:

• Improved control over the flow of current in the transistor.
• Reduction of leakage current, leading to lower power consumption.
• Enhanced performance and speed of semiconductor devices.
• Better integration of transistors in complex circuit designs.

Benefits of this technology:

• Higher performance and efficiency in semiconductor devices.
• Lower power consumption, leading to longer battery life in portable devices.
• Improved functionality and capabilities of electronic devices.
• Enables the development of smaller and more compact devices.

Abstract

A FinFET includes a semiconductor substrate, a semiconductor fin, a gate structure, and an isolation structure. The semiconductor fin protrudes from the semiconductor substrate. The gate structure is disposed across a first segment of the semiconductor fin. The isolation structure interrupts a continuity of a second segment of the semiconductor fin. The isolation structure has a first portion and a second portion stacked on the first portion. Sidewalls of the first portion are inclined and sidewalls of the second portion are straight. A top surface of the first portion is coplanar with a top surface of the gate structure.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17836399)

Main Inventor

Li-Zhen YU

Brief explanation

The patent application describes a semiconductor structure and a method for manufacturing it. The structure includes nanostructures, a gate structure, a source/drain structure, and a filling layer.

• The semiconductor structure includes nanostructures placed over a substrate.
• A gate structure surrounds the nanostructures and consists of gate dielectric layers and gate electrode layers.
• An inner spacer layer is located between the gate structure and the source/drain structure.
• A filling layer is present over the gate structure, with a protrusion portion embedded in a space surrounded by the inner spacer, gate dielectric layer, and gate electrode layer.
• A first source/drain contact structure is formed over the filling layer.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuits
• Transistors
• Electronic devices

Problems solved by this technology:

• Provides a structure that allows for efficient control of nanostructures and their surrounding components.
• Offers improved performance and functionality of semiconductor devices.
• Enhances the manufacturing process by providing a simplified and effective structure.

Benefits of this technology:

• Enables better control and manipulation of nanostructures.
• Enhances the performance and functionality of semiconductor devices.
• Simplifies the manufacturing process, leading to cost savings and improved efficiency.

Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures over a substrate, and a gate structure surrounding the nanostructures. The gate structure includes gate dielectric layers and gate electrode layers. The semiconductor structure also includes a source/drain (S/D) structure adjacent to the gate structure, and an inner spacer layer between the gate structure and the S/D structure. The semiconductor structure further includes a filling layer over the gate structure, and the filling layer has a protrusion portion embedded in a space, the space is surrounded by the inner spacer, the gate dielectric layer and the gate electrode layer. The semiconductor structure also includes a first S/D contact structure formed over the filling layer.

FORMING INTEGRATED ELECTRONIC DEVICES FOR CONVERTING AND DOWNSCALING ALTERNATING CURRENT (17806670)

Main Inventor

Yen-Ku LIN

Brief explanation

The patent application describes a method of reducing the chip area and power consumption of a power converter by bonding or integrating a full-bridge device and an LLC device together. This eliminates the need for connecting the devices with wires, saving raw materials and production time. The reduction in parasitic inductance and capacitance also contributes to lower power consumption.

• Bonding or integrating a full-bridge device and an LLC device in a stack or on the same substrate reduces chip area.
• This method reduces power consumption by reducing parasitic inductance and capacitance.
• Connecting the devices eliminates the need for wires, saving raw materials and production time.

Potential Applications

This technology can be applied in various power converter systems, such as:

• Renewable energy systems
• Electric vehicle charging systems
• Industrial power supplies
• Data centers

Problems Solved

The patent application addresses the following problems:

• Large chip area required for power converters
• High power consumption due to parasitic inductance and capacitance
• Raw material and production time wastage in connecting devices with wires

Benefits

The benefits of this technology include:

• Reduced chip area, leading to smaller and more compact power converters
• Lower power consumption, resulting in energy efficiency
• Conservation of raw materials and production time by eliminating the need for wire connections

Abstract

Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).

SYSTEMS AND METHODS FOR SUPPRESSING AND MITIGATING HARMONIC DISTORTION IN A CIRCUIT (18232343)

Main Inventor

Feng-Wei KUO

Brief explanation

The patent application describes systems and methods for reducing harmonic distortion in a circuit. Here is a simplified explanation of the abstract:

• The circuit includes an RF oscillator and a power amplifier.
• The RF oscillator generates an RF signal.
• The power amplifier amplifies the RF signal to generate an amplified RF signal.
• The power amplifier includes a transformer with primary and secondary windings.
• A feedback capacitor is connected to both the primary and secondary windings.

Potential Applications:

• This technology can be applied in various RF systems, such as wireless communication devices, radar systems, and satellite communication systems.
• It can be used in audio amplifiers, where harmonic distortion can affect sound quality.
• It can be implemented in power electronics systems to improve efficiency and reduce distortion.

Problems Solved:

• Harmonic distortion is a common issue in circuits, causing unwanted signals and reducing overall performance.
• This technology addresses the problem of harmonic distortion by providing a method to suppress and mitigate it.
• By using the feedback capacitor and transformer, the circuit can effectively reduce harmonic distortion.

Benefits:

• The circuit design helps to improve the overall performance of RF systems by reducing harmonic distortion.
• It enhances the quality of audio amplifiers by minimizing distortion and improving sound reproduction.
• The technology can lead to more efficient power electronics systems, reducing energy waste and improving power conversion efficiency.

Abstract

Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.

SYSTEM, METHOD, CIRCUIT, AND DEVICE FOR MILLIMETER-WAVE MULTI-STAGE AMPLIFIER WITH INDUCTIVE COUPLING (17836359)

Main Inventor

Wei Ling Chang

Brief explanation

The abstract describes a millimeter-wave amplifier circuit that includes two amplifiers and two inductors. The second inductor is electromagnetically coupled to the first inductor to send a signal in-phase with the output of the first amplifier.

• The millimeter-wave amplifier circuit includes two amplifiers and two inductors.
• The second inductor is coupled to the output of the first amplifier.
• The second amplifier is coupled to the output of the first amplifier.
• The second inductor electromagnetically couples to the first inductor.
• The second inductor sends a signal in-phase with the output of the first amplifier.

Potential Applications

• Wireless communication systems
• Radar systems
• Satellite communication systems

Problems Solved

• Improved signal amplification at millimeter-wave frequencies
• Efficient coupling of signals between amplifiers

Benefits

• Enhanced performance in millimeter-wave applications
• Increased signal strength and quality
• Improved overall system efficiency

Abstract

In some aspects of the present disclosure, a millimeter-wave amplifier circuit is disclosed. The millimeter-wave amplifier circuit includes a first amplifier, a first inductor coupled to an output of the first amplifier, a second amplifier coupled to the output of the first amplifier and a second inductor coupled to an output of the second amplifier. The second inductor electro-magnetically couples to the first inductor to send a first signal substantially in-phase with a second signal generated at the output of the first amplifier.

Semiconductor Devices And Circuits With Increased Breakdown Voltage (17835688)

Main Inventor

Yi-An Lai

Brief explanation

The patent application describes a switching circuit that includes a main circuit and an auxiliary circuit for surge protection. The main circuit has three nodes and is controlled by a control signal received at the first node. The second node receives a supply voltage.

• The main circuit includes a number of first transistors.
• The auxiliary circuit is electrically connected to the second node of the main circuit.
• The auxiliary circuit provides surge protection for the main circuit.
• The auxiliary circuit includes a second transistor.
• The breakdown voltage of the second transistor is different from the breakdown voltage of each first transistor.

Potential Applications

• Power distribution systems
• Electronic devices with switching circuits
• Surge protection in electrical circuits

Problems Solved

• Surge protection for the main circuit
• Preventing damage to the main circuit from voltage surges

Benefits

• Improved reliability of the switching circuit
• Enhanced protection against voltage surges
• Increased lifespan of the main circuit

Abstract

A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.

IMAGE SENSOR FOR SENSING LED LIGHT WITH REDUCED FLICKERING (18364873)

Main Inventor

Yun-Wei Cheng

Brief explanation

The patent application describes an image sensor device that has two sets of pixels, with the same number of pixels in each set. A light-blocking structure is placed over the pixels, with different sizes of openings for each set of pixels. A microcontroller is used to control the activation of the pixels in the second set at different times.

• The image sensor device has two sets of pixels with the same number of pixels in each set.
• A light-blocking structure is placed over the pixels to control the amount of light that reaches them.
• The light-blocking structure has different sizes of openings for each set of pixels.
• A microcontroller is used to selectively activate the pixels in the second set at different points in time.

Potential Applications

• This technology can be used in digital cameras and smartphones to improve image quality and dynamic range.
• It can also be applied in surveillance systems to capture clear images in varying lighting conditions.
• Medical imaging devices can benefit from this technology to enhance the accuracy of diagnostic imaging.

Problems Solved

• The light-blocking structure helps to reduce the amount of unwanted light that reaches the pixels, improving image quality.
• By selectively activating the pixels in the second set at different times, the device can capture a wider range of light intensities, resulting in better dynamic range.

Benefits

• Improved image quality and dynamic range in digital cameras and smartphones.
• Enhanced accuracy in medical imaging devices.
• Clearer images in surveillance systems.

Abstract

An image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. The first number is substantially equal to the second number. A light-blocking structure disposed over the first pixels and the second pixels. The light-blocking structure defines a plurality of first openings and second openings through which light can pass. The first openings are disposed over the first pixels. The second openings are disposed over the second pixels. The second openings are smaller than the first openings. A microcontroller is configured to turn on different ones of the second pixels at different points in time.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (17835769)

Main Inventor

Meng-Han Lin

Brief explanation

The patent application describes a semiconductor device that includes a memory structure and a test structure. The memory structure consists of multiple memory cells arranged in a specific pattern, while the test structure is located adjacent to the memory structure and includes a monitor pattern.

• The memory structure of the semiconductor device comprises multiple memory cells arranged in a specific pattern.
• The memory cells have channel films that extend vertically and share a ferroelectric film that extends vertically and laterally.
• The test structure, located next to the memory structure, includes a monitor pattern.
• The monitor pattern consists of a channel film and a ferroelectric film that extend vertically and laterally.

Potential applications of this technology:

• This semiconductor device can be used in various electronic devices that require memory storage, such as computers, smartphones, and tablets.
• The memory structure's unique arrangement and the inclusion of a test structure can improve the performance and reliability of the semiconductor device.

Problems solved by this technology:

• The specific arrangement of the memory cells and the inclusion of a test structure help in identifying and resolving any issues or defects in the memory structure.
• The use of a ferroelectric film in the memory cells can enhance the stability and durability of the memory structure.

Benefits of this technology:

• The semiconductor device with this memory structure can provide improved memory storage capabilities and performance.
• The inclusion of a test structure allows for easier testing and troubleshooting of the memory structure, leading to better quality control.
• The use of a ferroelectric film in the memory cells enhances the reliability and longevity of the semiconductor device.

Abstract

A semiconductor device includes a memory structure comprising a plurality of first memory cells. The semiconductor device includes a test structure disposed next to the memory structure and comprising a first monitor pattern. The plurality of first memory cells, arranged along a first lateral direction, that have a plurality of first channel films extending along a vertical direction, respectively, and share a first ferroelectric film extending along the vertical direction and the first lateral direction. The first monitor pattern includes: (a) a second channel film extending along the vertical direction and the first lateral direction; and (b) a second ferroelectric film extending along the vertical direction and the first lateral direction.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446043)

Main Inventor

Peng-Chun Liou

Brief explanation

The patent application describes a semiconductor device that consists of two conductive structures (first and second) extending vertically, with the second structure spaced apart from the first structure laterally. Additionally, there are multiple third conductive structures that extend laterally across the first and second structures. The first and second structures have varying widths along the lateral direction, and the third structures have different thicknesses corresponding to the varying widths of the first and second structures.

• The semiconductor device has a first and second conductive structure that extend vertically.
• The second conductive structure is laterally spaced apart from the first conductive structure.
• Multiple third conductive structures extend laterally across the first and second conductive structures.
• The first and second conductive structures have varying widths along the lateral direction.
• The third conductive structures have different thicknesses based on the varying widths of the first and second conductive structures.

Potential Applications:

• Integrated circuits
• Microprocessors
• Memory devices
• Power electronics
• Sensors

Problems Solved:

• Improved performance and efficiency of semiconductor devices
• Enhanced conductivity and electrical properties
• Better control of current flow and heat dissipation

Benefits:

• Increased functionality and versatility of semiconductor devices
• Improved power handling capabilities
• Enhanced reliability and durability
• Higher performance and efficiency
• Potential for miniaturization and cost reduction

Abstract

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.

EMBEDDED FERROELECTRIC FINFET MEMORY DEVICE (18364616)

Main Inventor

Bo-Feng Young

Brief explanation

The present disclosure describes a method of forming a ferroelectric memory device. The method involves forming a pair of source/drain regions in a substrate, followed by the formation of a gate dielectric and a gate electrode over the substrate and between the pair of source/drain regions. A polarization switching structure is then formed directly on the top surface of the gate electrode.

• The polarization switching structure is arranged directly on the gate electrode, allowing for a smaller pad size and more flexible area ratio tuning compared to traditional methods.
• Placing the polarization switching structure on top of the gate electrode also allows for better control of the quality of the ferroelectric structure, as the process of forming the gate electrode can withstand higher annealing temperatures.

Potential applications of this technology:

• Ferroelectric memory devices can be used in various electronic devices, such as smartphones, tablets, and computers, to store data.
• The smaller pad size and improved control of the ferroelectric structure quality can lead to more efficient and reliable memory devices.

Problems solved by this technology:

• Traditional methods of arranging the polarization switching structure under the gate electrode with aligned sidewalls and the same lateral dimensions can limit the flexibility and area ratio tuning of the device.
• The process of forming the gate electrode in traditional methods may not be able to withstand higher annealing temperatures, leading to lower quality ferroelectric structures.

Benefits of this technology:

• The method described in the patent allows for a smaller pad size and more flexible area ratio tuning, improving the overall efficiency and performance of the ferroelectric memory device.
• By placing the polarization switching structure directly on top of the gate electrode, the quality of the ferroelectric structure can be better controlled, leading to more reliable and durable memory devices.

Abstract

Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

FERROELECTRIC TUNNEL JUNCTIONS WITH CONDUCTIVE ELECTRODES HAVING ASYMMETRIC NITROGEN OR OXYGEN PROFILES (17834939)

Main Inventor

Yi-Hsuan Chen

Brief explanation

The patent application describes a semiconductor device that includes a ferroelectric tunnel junction (FTJ). The FTJ consists of a first electrode, a ferroelectric layer, and a second electrode. The first electrode contains nitrogen or oxygen and has a certain percentage of nitrogen or oxygen, while the second electrode also contains nitrogen or oxygen but has a different percentage.

• The semiconductor device includes a ferroelectric tunnel junction (FTJ).
• The FTJ consists of a first electrode, a ferroelectric layer, and a second electrode.
• The first electrode contains nitrogen or oxygen and has a specific percentage of nitrogen or oxygen.
• The second electrode contains nitrogen or oxygen and has a different percentage of nitrogen or oxygen.

Potential applications of this technology:

• Memory devices: The ferroelectric tunnel junction can be used in non-volatile memory devices, such as FeRAM (ferroelectric random-access memory), due to its ability to retain information even when power is turned off.
• Logic devices: The semiconductor device can be utilized in logic circuits, enabling low-power and high-speed operations.
• Sensor devices: The ferroelectric tunnel junction can be employed in sensor devices for various applications, such as pressure sensors or temperature sensors.

Problems solved by this technology:

• Non-volatility: The ferroelectric tunnel junction provides a solution for developing non-volatile memory devices that can retain data without the need for continuous power supply.
• Low-power operation: The semiconductor device allows for low-power operation, reducing energy consumption and extending battery life in portable devices.
• High-speed operation: The technology enables high-speed operation in logic circuits, improving overall device performance.

Benefits of this technology:

• Improved memory performance: The ferroelectric tunnel junction offers enhanced memory performance, including faster read and write operations, high endurance, and low power consumption.
• Versatile applications: The semiconductor device can be utilized in various applications, including memory devices, logic circuits, and sensor devices, providing flexibility and adaptability.
• Compatibility: The technology can be integrated into existing semiconductor manufacturing processes, making it compatible with current fabrication techniques.

Abstract

A semiconductor device includes a ferroelectric tunnel junction (FTJ), wherein the ferroelectric tunnel junction includes a first electrode, a ferroelectric layer disposed over the first electrode, and a second electrode disposed over the ferroelectric layer. The first electrode contains nitrogen or oxygen and is characterized by a first percentage of nitrogen or oxygen. The second electrode contains nitrogen or oxygen and is characterized by a second percentage of nitrogen or oxygen. The first percentage is different from the second percentage.

SEMICONDUCTOR DEVICES (17835988)

Main Inventor

Ying-Chih Chen

Brief explanation

The patent application describes a semiconductor device that consists of three layers: a first electrode layer, a ferroelectric layer, and a second electrode layer. The ferroelectric layer is made up of a ferroelectric material that is doped with two different dopants, one of which is cerium. This layer is positioned between the two electrode layers.

• The ferroelectric layer in the semiconductor device is doped with cerium and another dopant, which enhances its properties and performance.
• The use of cerium as a dopant in the ferroelectric material improves the functionality of the semiconductor device.
• The ferroelectric layer is sandwiched between two electrode layers, providing a structure that can be utilized in various electronic applications.

Potential Applications

• Memory devices: The semiconductor device can be used in non-volatile memory applications, such as ferroelectric random-access memory (FeRAM) or ferroelectric field-effect transistors (FeFETs).
• Sensors: The device can be employed in sensors that require high sensitivity and stability, such as pressure sensors or temperature sensors.
• Energy storage: The ferroelectric layer can be utilized in energy storage devices, such as capacitors or batteries, due to its ability to retain charge.

Problems Solved

• Enhanced performance: The use of cerium and another dopant in the ferroelectric layer improves the functionality and performance of the semiconductor device.
• Stability: The ferroelectric layer provides stability to the device, allowing it to retain its properties over time.
• Compatibility: The device can be integrated into existing electronic systems and circuits due to its compatibility with standard semiconductor fabrication processes.

Benefits

• Improved functionality: The doping of the ferroelectric layer with cerium and another dopant enhances the performance and functionality of the semiconductor device.
• Versatility: The device can be utilized in various electronic applications, including memory devices, sensors, and energy storage.
• Compatibility: The semiconductor device can be easily integrated into existing electronic systems and circuits, making it a practical solution for different industries.

Abstract

A semiconductor device includes a first electrode layer, a ferroelectric layer, and a second electrode layer. A material of the ferroelectric layer comprises a ferroelectric material doped with a first dopant and a second dopant different from the first dopant, and the first dopant comprises cerium. The ferroelectric layer is disposed between the first electrode layer and the second electrode layer.

FERROELECTRIC TUNNEL JUNCTION MEMORY DEVICES WITH ENHANCED READ WINDOW (17840003)

Main Inventor

Wei Ting HSIEH

Brief explanation

The patent application describes a semiconductor device that uses a ferroelectric film to alter the effective resistance through the device. This is achieved by applying different voltages across the device.

• The device includes a first capacitor with a ferroelectric film between two electrodes.
• A first voltage is applied to polarize the ferroelectric film, changing the resistance.
• A second voltage is applied to cause a leakage current to accumulate along an electrode of a second capacitor and the gate of a transistor.
• This accumulation affects the drain to source resistance of the transistor, which can be measured to determine the polarization state of the ferroelectric film.

Potential Applications

• Memory devices: The ability to measure the polarization state of the ferroelectric film can be used in non-volatile memory applications.
• Sensor devices: The change in resistance can be utilized in sensor devices for various applications such as pressure, temperature, or gas sensing.

Problems Solved

• Non-volatile memory: The ability to determine the polarization state of the ferroelectric film allows for reliable and efficient non-volatile memory storage.
• Sensor accuracy: The change in resistance can provide more accurate and sensitive measurements in sensor devices.

Benefits

• Improved memory performance: The use of ferroelectric film allows for faster and more efficient memory operations.
• Enhanced sensor sensitivity: The change in resistance provides higher sensitivity and accuracy in sensor measurements.
• Compact design: The semiconductor device can be integrated into a compact form factor, making it suitable for various applications.

Abstract

A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE (18447614)

Main Inventor

Jerry Chang Jui KAO

Brief explanation

The patent application describes a method for forming a circuit region on a substrate, with active and gate regions. It also involves forming input/output patterns in different metal layers to connect the circuit region to external circuitry. The input/output patterns extend in oblique directions to the active and gate regions.

• The method involves forming a circuit region on a substrate.
• The circuit region includes active and gate regions.
• Input/output patterns are formed in different metal layers.
• The input/output patterns connect the circuit region to external circuitry.
• The first input/output pattern extends obliquely in a third direction.
• The second input/output pattern extends obliquely in a fourth direction.
• The fourth direction is transverse to the third direction.

Potential applications of this technology:

• Integrated circuits
• Semiconductor devices
• Electronic components

Problems solved by this technology:

• Simplifies the formation of circuit regions on a substrate
• Provides efficient electrical coupling to external circuitry

Benefits of this technology:

• Improved circuit integration
• Enhanced performance of semiconductor devices
• Simplified manufacturing process

Abstract

A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICES AND METHODS OF FORMING THE SAME (17838235)

Main Inventor

Hsuan-Yi PENG

Brief explanation

The abstract describes a magnetic tunnel junction (MTJ) structure for data storage. The structure includes multiple layers and metal particles distributed in a discrete and non-continuous manner. 

• The MTJ structure consists of a first ferromagnetic layer, a second ferromagnetic layer, and a first dielectric layer between them.
• Metal particles are present in contact with the second ferromagnetic layer, but they are distributed in a discrete and non-continuous manner.
• A second dielectric layer is placed over the metal particles.

Potential applications of this technology:

• Data storage devices: The MTJ structure can be used in magnetic storage devices such as hard disk drives and magnetic random-access memory (MRAM) to store data.
• Spintronics: The MTJ structure can be utilized in spintronic devices for various applications, including logic circuits and magnetic sensors.

Problems solved by this technology:

• Data storage density: The discrete and non-continuous distribution of metal particles allows for higher data storage density, as it enables more efficient use of space within the MTJ structure.
• Stability: The presence of the metal particles enhances the stability of the MTJ structure, reducing the likelihood of data loss or corruption.

Benefits of this technology:

• Increased data storage capacity: The improved density achieved through the discrete distribution of metal particles allows for higher data storage capacity in the same physical space.
• Enhanced data stability: The presence of metal particles improves the stability of the MTJ structure, ensuring reliable data storage and reducing the risk of data loss.
• Compatibility: The MTJ structure can be integrated into existing data storage technologies, making it compatible with current systems and devices.

Abstract

Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF FORMING THE SAME (17838166)

Main Inventor

Chin I WANG

Brief explanation

The abstract describes a memory device and methods of forming it. The memory device includes a substrate, a bottom electrode, a top electrode, and a phase change layer. The phase change layer is a laminated structure with alternating layers of different phase change materials.

• The memory device includes a substrate, bottom electrode, top electrode, and a phase change layer.
• The phase change layer is a laminated structure with alternating layers of different phase change materials.
• The first layer of phase change material is chemically different from the second layer.
• The first layer of phase change material is thinner than the second layer.

Potential applications of this technology:

• Memory devices in electronic devices such as computers, smartphones, and tablets.
• Non-volatile memory for data storage in various industries including automotive, aerospace, and healthcare.

Problems solved by this technology:

• Provides a memory device with improved performance and reliability.
• Allows for more efficient data storage and retrieval.
• Reduces power consumption and heat generation.

Benefits of this technology:

• Enhanced memory device performance.
• Increased data storage capacity.
• Improved energy efficiency.

Abstract

Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and the bottom electrode. The phase change layer is a laminated structure comprising a first layer of phase change material and a second layer of phase change material alternatingly stacked, and the first layer of phase change material is chemically different from the second layer of phase change material, wherein the first layer of phase change material has a first thickness that is less than a second thickness of the second layer of phase change material.