17806311. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chih-Ju Yen of New Taipei City (TW)
Jui Hsien Lo of New Taipei City (TW)
Chien-Sheng Chen of Hsinchu City (TW)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17806311 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING
Simplified Explanation
The patent application describes a semiconductor package that includes an integrated circuit die mounted to an interposer using connection structures. The package also includes an underfill material between the die and the interposer, which includes shaped fillets that are below the bottom surface of the die. These shaped fillets help reduce the likelihood of stresses and strains that could damage the mold compound from transferring to the mold compound from the underfill material, die, and interposer. This improves the quality and reliability of the semiconductor package, potentially increasing the yield and decreasing the cost.
- Semiconductor package includes an integrated circuit die mounted to an interposer using connection structures.
- Underfill material between the die and the interposer includes shaped fillets below the bottom surface of the die.
- Shaped fillets reduce the likelihood of stresses and strains damaging the mold compound.
- Improved quality and reliability of the semiconductor package.
- Potential increase in yield and decrease in cost of the semiconductor package.
Potential Applications
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit packaging industry
Problems Solved
- Reduces the likelihood of stresses and strains damaging the mold compound.
- Improves the quality and reliability of the semiconductor package.
Benefits
- Increased yield of the semiconductor package.
- Decreased cost of the semiconductor package.
Original Abstract Submitted
Some implementations described herein provide a semiconductor package including an integrated circuit die mounted to an interposer using connection structures. An underfill material between the integrated circuit die and the interposer includes shaped fillets that are below a plane corresponding to a bottom surface of the integrated circuit die. The underfill material including the shaped fillets reduces a likelihood of stresses and/or strains that damage a mold compound from transferring to the mold compound from the underfill material, the integrated circuit die, and/or the interposer. In this way, a quality and reliability of the semiconductor package including the underfill material with the shaped fillets is reduced. By improving the quality and reliability of the semiconductor package, a yield of the semiconductor package may increase to decrease a cost of the semiconductor package.
