18177409. Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Szu-Hua Chen of Tainan City (TW)

Cheng-Ming Lin of Kaohsuing City (TW)

Wei-Xiang You of Kaohsuing City (TW)

Wei-De Ho of Hsinchu City (TW)

Wei-Yen Woon of Taoyuan City (TW)

Szuya Liao of Zhubei Hsinchu (TW)

Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18177409 titled 'Semiconductor Structures With Reduced Parasitic Capacitance And Methods For Forming The Same

Simplified Explanation

The patent application describes a method for forming semiconductor structures using a dummy gate stack and gate spacers. The method involves depositing two dielectric layers, etching them back to form gate spacers, and then replacing the dummy gate stack with a gate structure. The dielectric layers have specific properties to enhance the performance of the semiconductor structure.

• The method involves forming a dummy gate stack on a semiconductor fin over a substrate.
• Two dielectric layers are conformally deposited over the substrate.
• The first dielectric layer has a lower dielectric constant than silicon oxide.
• The second dielectric layer is less easily oxidized than the first dielectric layer.
• The first and second dielectric layers are etched back to form gate spacers along the sidewall of the dummy gate stack.
• Source/drain features are formed in and over the semiconductor fin adjacent to the dummy gate stack.
• The dummy gate stack is then replaced with a gate structure.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuit fabrication
• Transistor design and production

Problems solved by this technology:

• Enhances the performance and efficiency of semiconductor structures
• Improves the reliability and stability of gate spacers
• Reduces the risk of oxidation during fabrication

Benefits of this technology:

• Improved transistor performance
• Enhanced integration density
• Increased reliability and stability of semiconductor structures

Original Abstract Submitted

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.