17839946. Wafer Level Multi-Die Structure Formation simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
Wafer Level Multi-Die Structure Formation
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Shan-Yu Huang of Zhubei city (TW)
Shih-Chang Chen of Chiayi County (TW)
Huang-Sheng Lin of Hsin-Chu (TW)
Wafer Level Multi-Die Structure Formation - A simplified explanation of the abstract
This abstract first appeared for US patent application 17839946 titled 'Wafer Level Multi-Die Structure Formation
Simplified Explanation
The patent application describes a method for arranging an array of dies on a substrate, where each die contains multiple functional transistors. The dies are surrounded by first seal rings, which define corner regions between subsets of the dies. Within these corner regions, various structures such as test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks are placed. Electrical interconnection elements are used to connect adjacent dies in the array. The entire array, including the dies, seal rings, structures, and interconnection elements, is then surrounded by a second seal ring.
- An array of dies is formed on a substrate, with each die containing multiple functional transistors.
- First seal rings are placed around each die, creating corner regions between subsets of the dies.
- Structures such as test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks are placed within the corner regions.
- Electrical interconnection elements are used to connect adjacent dies in the array.
- A second seal ring surrounds the entire array, including the dies, seal rings, structures, and interconnection elements.
Potential Applications
- Semiconductor manufacturing
- Integrated circuit design
- Electronics industry
Problems Solved
- Efficient arrangement of dies on a substrate
- Electrical interconnection between adjacent dies
- Integration of various structures within the corner regions
Benefits
- Improved functionality and performance of integrated circuits
- Enhanced manufacturing efficiency and yield
- Better alignment and overlay accuracy in semiconductor processes
Original Abstract Submitted
An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.
