17839292. Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
- 1 Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Abstract
- 1.6 Patent/Innovation Explanation
- 1.7 Potential Applications
- 1.8 Problems Solved
- 1.9 Benefits
- 1.10 Original Abstract Submitted
Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Shan-Yu Huang of Zhubei city (TW)
Huang-Sheng Lin of Hsin-Chu (TW)
Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures - A simplified explanation of the abstract
This abstract first appeared for US patent application 17839292 titled 'Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures
Simplified Explanation
Abstract
The patent application describes a structure that includes two dies with transistors and conductive elements that interconnect them. The dies are surrounded by seal rings for protection.
Patent/Innovation Explanation
- The structure includes two dies with transistors.
- Each die is surrounded by a seal ring in the top view.
- Conductive elements extend into both dies and interconnect them.
- A third seal ring surrounds both dies and the conductive elements.
Potential Applications
- Integrated circuits
- Semiconductor devices
- Electronics manufacturing
Problems Solved
- Provides a structure for interconnecting multiple dies in a compact manner.
- Protects the dies and conductive elements with seal rings.
Benefits
- Enables efficient integration of multiple dies in a single structure.
- Enhances the reliability and durability of the interconnected dies.
- Simplifies the manufacturing process for electronic devices.
Original Abstract Submitted
A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.
