18150474. Transistor Gate Structures and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

Transistor Gate Structures and Methods of Forming the Same

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chung-Wei Hsu of Baoshan Township (TW)

Kuan-Ting Pan of Taipei City (TW)

Lung-Kun Chu of New Taipei City (TW)

Kuo-Cheng Chiang of Zhubei City (TW)

Chih-Hao Wang of Baoshan Township (TW)

Jia-Ni Yu of New Taipei City (TW)

Transistor Gate Structures and Methods of Forming the Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18150474 titled 'Transistor Gate Structures and Methods of Forming the Same

Simplified Explanation

The patent application describes a device with nanostructures and gate spacers on a substrate, along with a dielectric wall between them. The gate structure surrounds the nanostructures and fills the areas between the dielectric wall and the nanostructures.

• The device includes an isolation region on a substrate.
• There are first and second nanostructures above the isolation region.
• First and second gate spacers are present on the respective nanostructures.
• A dielectric wall separates the gate spacers along one direction and the nanostructures along another direction.
• The gate structure surrounds the nanostructures and fills the areas between the dielectric wall and the nanostructures.

Potential Applications

• This technology can be used in the development of advanced electronic devices.
• It may find applications in the field of nanoelectronics and semiconductor industry.

Problems Solved

• The device provides improved isolation between the nanostructures and gate spacers.
• It allows for better control and manipulation of the electrical properties of the nanostructures.

Benefits

• The device offers enhanced performance and functionality in electronic devices.
• It enables more efficient use of space and resources in the fabrication process.
• The technology may lead to the development of smaller and more powerful electronic devices.

Original Abstract Submitted

In an embodiment, a device includes: an isolation region on a substrate; first nanostructures above the isolation region; second nanostructures above the isolation region; a first gate spacer on the first nanostructures; a second gate spacer on the second nanostructures; a dielectric wall between the first gate spacer and the second gate spacer along a first direction in a top-down view, the dielectric wall disposed between the first nanostructures and the second nanostructures along a second direction in the top-down view, the first direction perpendicular to the second direction; and a gate structure around the first nanostructures and around the second nanostructures, a first portion of the gate structure filling a first area between the dielectric wall and the first nanostructures, a second portion of the gate structure filling a second area between the dielectric wall and the second nanostructures.