18230664. MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Feng-Chien Hsieh of Pingtung County (TW)
Ting-Hao Chang of Hsinchu (TW)
MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18230664 titled 'MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING
Simplified Explanation
The patent application describes a method of manufacturing a semiconductor wafer. Here is a simplified explanation of the abstract:
- The method involves exposing the semiconductor wafer to dopant species, which are substances that introduce impurities into the semiconductor material.
- This exposure forms one or more first implant layers on the semiconductor wafer.
- The geometric parameter values of the first implant layers are then tested.
- Based on the test results, the semiconductor wafer is conditionally exposed to additional dopant species to form one or more additional implant layers.
- After forming the additional implant layers, one or more additional circuit layers are conditionally formed on the semiconductor wafer, resulting in the creation of multiple functional electronic circuits.
- Finally, the semiconductor wafer is conditionally tested using a wafer acceptance test (WAT) operation.
Potential applications of this technology:
- Semiconductor manufacturing industry
- Electronics manufacturing industry
Problems solved by this technology:
- Provides a method for manufacturing semiconductor wafers with multiple functional electronic circuits.
- Allows for conditional exposure to dopant species based on the test results of the first implant layers, ensuring optimal performance of the circuits.
Benefits of this technology:
- Efficient manufacturing process for semiconductor wafers with multiple circuits.
- Improved quality control through conditional testing and exposure to dopant species.
- Enables the production of high-performance electronic devices.
Original Abstract Submitted
A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.
