18447682. SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Wei-Ling Chang of Hsinchu (TW)
Chih-Liang Chen of Hsinchu (TW)
SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447682 titled 'SIGNAL CONDUCTING LINE ARRANGEMENTS IN INTEGRATED CIRCUITS
Simplified Explanation
The patent application describes a method for fabricating semiconductor structures and gate-conductors to create a circuit cell. It involves patterning metal layers to form horizontal and vertical conducting lines, which are connected through pin-connectors.
- The method involves fabricating semiconductor structures and gate-conductors.
- Metal layers are patterned to create horizontal and vertical conducting lines.
- Vertical conducting lines are aligned with gate-conductors and circuit cell boundaries.
- Pin-connectors directly connect vertical and horizontal conducting lines.
Potential Applications
This technology can be applied in various fields that utilize semiconductor devices, such as:
- Integrated circuits
- Microprocessors
- Memory devices
- Power electronics
Problems Solved
The technology addresses the following problems in semiconductor fabrication:
- Efficiently connecting vertical and horizontal conducting lines.
- Aligning vertical conducting lines with gate-conductors and circuit cell boundaries.
- Simplifying the fabrication process.
Benefits
The use of this technology offers several benefits:
- Improved electrical connectivity between vertical and horizontal conducting lines.
- Enhanced alignment accuracy between vertical conducting lines and gate-conductors.
- Streamlined fabrication process for semiconductor structures.
- Potential for increased performance and reliability of semiconductor devices.
Original Abstract Submitted
A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.
