18232341. NOVEL JITTER NOISE DETECTOR simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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NOVEL JITTER NOISE DETECTOR

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Tien-Chien Huang of Hsinchu City (TW)

NOVEL JITTER NOISE DETECTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232341 titled 'NOVEL JITTER NOISE DETECTOR

Simplified Explanation

The abstract describes a noise detection circuit that includes transistors and a latch circuit to detect timing differences between clock signals. Here is a simplified explanation of the abstract:

  • The noise detection circuit consists of a first transistor that receives a delayed version of a clock signal and a second transistor that receives a delayed version of a reference clock signal.
  • The circuit also includes a latch circuit that is connected to the first transistor at a first node and to the second transistor at a second node.
  • The latch circuit is designed to latch the logic states of voltage levels at the first and second nodes based on whether the timing difference between the transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

Potential applications of this technology:

  • Noise detection circuits can be used in various electronic devices and systems where accurate timing is crucial, such as communication systems, data storage devices, and digital signal processing.
  • It can be used in high-speed data transmission systems to detect and mitigate noise or interference that can affect the integrity of the transmitted data.
  • The circuit can also be used in clock synchronization systems to ensure precise timing between different components or subsystems.

Problems solved by this technology:

  • The noise detection circuit addresses the problem of timing discrepancies between clock signals and reference signals, which can lead to errors or malfunctions in electronic systems.
  • By detecting and latching the logic states of voltage levels based on timing differences, the circuit can identify and mitigate noise or interference that can disrupt the proper functioning of electronic devices.

Benefits of this technology:

  • The circuit provides a reliable and efficient method for detecting and addressing timing discrepancies in electronic systems.
  • It allows for accurate synchronization of clock signals, ensuring the proper operation of electronic devices.
  • By detecting and mitigating noise or interference, the circuit helps improve the overall performance and reliability of electronic systems.


Original Abstract Submitted

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

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