Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on May 18th, 2023
Summary of the patent applications from Taiwan Semiconductor Manufacturing Co., Ltd. on May 18th, 2023
Taiwan Semiconductor Manufacturing Co., Ltd. has filed several recent patents related to memory devices and integrated circuits. These patents focus on improving the performance, efficiency, and functionality of memory cells and integrated chip structures.
One patent describes a memory device with a unique structure that includes a bit line, word line, memory cell, select bit lines, and a controller. The memory cell consists of a first transistor, data storage elements, and second transistors. The controller activates the first transistor and a selected second transistor, and different voltages are applied to the bit line to perform operations on the data storage element connected to the selected second transistor.
Another patent describes an integrated chip structure with a memory array and local interconnects. The memory array is arranged in rows and columns, and the local interconnects provide efficient connectivity between the memory devices and the bit line. This design allows for higher memory density and improved data transfer and access speeds.
Another patent focuses on an integrated chip with a memory cell within a metal interconnect. This design saves space and improves integration, leading to increased memory storage capacity and lower threshold voltages.
Another patent describes a memory device with a unique configuration that includes multiple transistors with semiconductor nanostructures. This design enables higher storage capacity, improved performance, and reduced physical size of memory devices.
Other patents include an integrated circuit with fuse elements, an integrated circuit with various components and structures for electrical connection, a memory cell with stress-induced nanostructures, and a digitally controlled delay line for adjustable signal delay.
Notable applications of these patents include memory devices for computers, smartphones, and other electronic devices, high-speed data storage and retrieval systems, solid-state drives (SSDs), and flash memory devices.
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on May 18th, 2023
- 1.1 Deposition Apparatus and Method (17674977)
- 1.2 CHAMBER WALL POLYMER PROTECTION SYSTEM AND METHOD (17679537)
- 1.3 METHODS OF FORMING PHOTONIC DEVICES (18094839)
- 1.4 PHOTONIC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (17567497)
- 1.5 EUV MASKS TO PREVENT CARBON CONTAMINATION (18151416)
- 1.6 METHODS FOR CLEANING LITHOGRAPHY MASK (17690150)
- 1.7 METHOD OF OPERATING SEMICONDUCTOR APPARATUS (18153708)
- 1.8 METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION (18151527)
- 1.9 BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS (18096906)
- 1.10 CELL LAYOUT OF SEMICONDUCTOR DEVICE (18156912)
- 1.11 INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEM (18156671)
- 1.12 BIT LINE LOGIC CIRCUITS AND METHODS (18153464)
- 1.13 STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE (18156707)
- 1.14 MEMORY CIRCUIT AND METHOD OF OPERATING SAME (18155925)
- 1.15 INTEGRATED CIRCUIT HAVING CURRENT-SENSING COIL (18156657)
- 1.16 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17824129)
- 1.17 Photoresist and Method (17674575)
- 1.18 Patterned Semiconductor Device and Method (17686184)
- 1.19 CONTACT STRUCTURES WITH DEPOSITED SILICIDE LAYERS (18097323)
- 1.20 Reduction of Line Wiggling (18156123)
- 1.21 Semiconductor Device and Method of Forming the Same (17739783)
- 1.22 Staggered Metal Mesh on Backside of Device Die and Method Forming Same (17655645)
- 1.23 Oxygen-Free Protection Layer Formation in Wafer Bonding Process (17651329)
- 1.24 SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION CAP (18154540)
- 1.25 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18097418)
- 1.26 INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME (17679234)
- 1.27 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (18151412)
- 1.28 Method and Structure for FinFET Isolation (18157352)
- 1.29 FINFET EPI CHANNELS HAVING DIFFERENT HEIGHTS ON A STEPPED SUBSTRATE (18149495)
- 1.30 SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (17526774)
- 1.31 SEMICONDUCTOR PACKAGES WITH SHORTENED TALKING PATH (18155713)
- 1.32 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (18150552)
- 1.33 Wafer Bonding Incorporating Thermal Conductive Paths (17651665)
- 1.34 PACKAGE STRUCTURE WITH THROUGH VIAS (18157509)
- 1.35 CELL HAVING STACKED PICK-UP REGION (18155914)
- 1.36 Semiconductor Device with Integrated Metal-Insulator-Metal Capacitors (17674459)
- 1.37 Interconnect Structures (18149477)
- 1.38 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE (18156752)
- 1.39 LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS (18156086)
- 1.40 Forming Dielectric Film With High Resistance to Tilting (17651990)
- 1.41 SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION STRUCTURE AND MANUFACTURING METHOD THEREOF (18155672)
- 1.42 DUAL SIDE SEAL RINGS (17708852)
- 1.43 Redistribution Lines Having Nano Columns and Method Forming Same (18151014)
- 1.44 PACKAGE STRUCTURE INCLUDING IPD AND METHOD OF FORMING THE SAME (18155705)
- 1.45 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (17669914)
- 1.46 3D Package Structure and Methods of Forming Same (18149509)
- 1.47 3DIC STRUCTURE AND METHODS OF FORMING (18156848)
- 1.48 Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits (17650758)
- 1.49 METHOD AND STRUCTURE FOR 3DIC POWER DISTRIBUTION (17703700)
- 1.50 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18155536)
- 1.51 NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD (18156605)
- 1.52 AIR SPACER AND CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES (18158036)
- 1.53 Integration of Multiple Transistors Having Fin and Mesa Structures (17655321)
- 1.54 DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF (17677929)
- 1.55 FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME (18149128)
- 1.56 CAPACITOR DEVICE WITH MULTI-LAYER DIELECTRIC STRUCTURE (17569279)
- 1.57 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18097057)
- 1.58 Transistor Isolation Regions and Methods of Forming the Same (17742943)
- 1.59 ARRANGEMENT OF SOURCE OR DRAIN CONDUCTORS OF TRANSISTOR (17525173)
- 1.60 SILICIDE-SANDWICHED SOURCE/DRAIN REGION AND METHOD OF FABRICATING SAME (18155887)
- 1.61 Isolation Layers for Reducing Leakages Between Contacts (17651671)
- 1.62 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18100302)
- 1.63 Dual Damascene Structure in Forming Source/Drain Contacts (17651347)
- 1.64 METAL GATE FIN ELECTRODE STRUCTURE AND METHOD (17700998)
- 1.65 STRUCTURE OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE (18157395)
- 1.66 TRANSISTOR SOURCE/DRAIN CONTACTS AND METHODS OF FORMING THE SAME (17651721)
- 1.67 SEMICONDUCTOR DEVICE AND METHOD (17663278)
- 1.68 Semiconductor Device and Method (17744061)
- 1.69 FIN PROFILE MODULATION (17836628)
- 1.70 Gate All Around Transistor Device and Fabrication Methods Thereof (18155392)
- 1.71 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES (17569057)
- 1.72 SEMICONDUCTOR DEVICE (18157906)
- 1.73 DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD (18155906)
- 1.74 FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME (18155932)
- 1.75 MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18157461)
- 1.76 ANTI-FUSE DEVICE AND METHOD (18156625)
- 1.77 INTEGRATED CIRCUIT INCLUDING EFUSE CELL (18156978)
- 1.78 MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18157418)
- 1.79 THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18155688)
- 1.80 TRENCH-TYPE BEOL MEMORY CELL (17672382)
- 1.81 BIT-LINE RESISTANCE REDUCTION (17690728)
- 1.82 MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD (18156734)
Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on May 18th, 2023
Deposition Apparatus and Method (17674977)
Main Inventor
Tze-Liang Lee
CHAMBER WALL POLYMER PROTECTION SYSTEM AND METHOD (17679537)
Main Inventor
Po-Hsun Tseng
METHODS OF FORMING PHOTONIC DEVICES (18094839)
Main Inventor
Tao-Cheng LIU
PHOTONIC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (17567497)
Main Inventor
Chung-Ming Weng
EUV MASKS TO PREVENT CARBON CONTAMINATION (18151416)
Main Inventor
Pei-Cheng HSU
METHODS FOR CLEANING LITHOGRAPHY MASK (17690150)
Main Inventor
I-Hsiung HUANG
METHOD OF OPERATING SEMICONDUCTOR APPARATUS (18153708)
Main Inventor
Shih-Ming CHANG
METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION (18151527)
Main Inventor
Cheng-Kuan WU
BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS (18096906)
Main Inventor
Yen-Hung Lin
CELL LAYOUT OF SEMICONDUCTOR DEVICE (18156912)
Main Inventor
Yi-Lin CHUANG
INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEM (18156671)
Main Inventor
Ya-Min ZHANG
BIT LINE LOGIC CIRCUITS AND METHODS (18153464)
Main Inventor
Shang-Chi WU
STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE (18156707)
Main Inventor
Hiroki NOGUCHI
MEMORY CIRCUIT AND METHOD OF OPERATING SAME (18155925)
Main Inventor
Chun-Hao CHANG
INTEGRATED CIRCUIT HAVING CURRENT-SENSING COIL (18156657)
Main Inventor
Alan ROTH
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (17824129)
Main Inventor
Wan-Yi KAO
Photoresist and Method (17674575)
Main Inventor
Chih-Cheng Liu
Patterned Semiconductor Device and Method (17686184)
Main Inventor
Jung-Hau Shiu
CONTACT STRUCTURES WITH DEPOSITED SILICIDE LAYERS (18097323)
Main Inventor
Sung-Li WANG
Reduction of Line Wiggling (18156123)
Main Inventor
Jiann-Horng Lin
Semiconductor Device and Method of Forming the Same (17739783)
Main Inventor
Po-Wei Hu
Staggered Metal Mesh on Backside of Device Die and Method Forming Same (17655645)
Main Inventor
Tzu-Sung Huang
Oxygen-Free Protection Layer Formation in Wafer Bonding Process (17651329)
Main Inventor
Chia Cheng Chou
SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION CAP (18154540)
Main Inventor
Ting-Li YANG
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18097418)
Main Inventor
Hsin-Yen HUANG
INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME (17679234)
Main Inventor
Chin-Lung Chung
METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE (18151412)
Main Inventor
Chen-Cheng CHOU
Method and Structure for FinFET Isolation (18157352)
Main Inventor
Che-Cheng Chang
FINFET EPI CHANNELS HAVING DIFFERENT HEIGHTS ON A STEPPED SUBSTRATE (18149495)
Main Inventor
Cheng-Han Lee
SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (17526774)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR PACKAGES WITH SHORTENED TALKING PATH (18155713)
Main Inventor
Hsien-Wei Chen
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (18150552)
Main Inventor
Hung-Chun Cho
Wafer Bonding Incorporating Thermal Conductive Paths (17651665)
Main Inventor
Su-Jen Sung
PACKAGE STRUCTURE WITH THROUGH VIAS (18157509)
Main Inventor
Ling-Wei LI
CELL HAVING STACKED PICK-UP REGION (18155914)
Main Inventor
Chung-Hui CHEN
Semiconductor Device with Integrated Metal-Insulator-Metal Capacitors (17674459)
Main Inventor
Wei-Zhong Chen
Interconnect Structures (18149477)
Main Inventor
Sung-Li Wang
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE (18156752)
Main Inventor
Te-Hsin CHIU
LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS (18156086)
Main Inventor
Wan-Yu LO
Forming Dielectric Film With High Resistance to Tilting (17651990)
Main Inventor
Ming-Tsung Lee
SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION STRUCTURE AND MANUFACTURING METHOD THEREOF (18155672)
Main Inventor
Wei-Cheng Wu
DUAL SIDE SEAL RINGS (17708852)
Main Inventor
Chun Yu Chen
Redistribution Lines Having Nano Columns and Method Forming Same (18151014)
Main Inventor
Po-Hao Tsai
PACKAGE STRUCTURE INCLUDING IPD AND METHOD OF FORMING THE SAME (18155705)
Main Inventor
Hua-Wei Tseng
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (17669914)
Main Inventor
Yen-Chu TU
3D Package Structure and Methods of Forming Same (18149509)
Main Inventor
Meng-Tse Chen
3DIC STRUCTURE AND METHODS OF FORMING (18156848)
Main Inventor
Kuo-Ming Wu
Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits (17650758)
Main Inventor
Chan-Hong Chern
METHOD AND STRUCTURE FOR 3DIC POWER DISTRIBUTION (17703700)
Main Inventor
Chung-Hao Tsai
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18155536)
Main Inventor
Shih-Wei PENG
NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD (18156605)
Main Inventor
Chih-Liang CHEN
AIR SPACER AND CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES (18158036)
Main Inventor
Lin-Yu Huang
Integration of Multiple Transistors Having Fin and Mesa Structures (17655321)
Main Inventor
Sung-Hsin Yang
DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF (17677929)
Main Inventor
Shih-Ya LIN
FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME (18149128)
Main Inventor
Te-Hsin Chiu
CAPACITOR DEVICE WITH MULTI-LAYER DIELECTRIC STRUCTURE (17569279)
Main Inventor
Yu-En JENG
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18097057)
Main Inventor
Chun Hsiung TSAI
Transistor Isolation Regions and Methods of Forming the Same (17742943)
Main Inventor
Chung-Ting Ko
ARRANGEMENT OF SOURCE OR DRAIN CONDUCTORS OF TRANSISTOR (17525173)
Main Inventor
Chih-Yu LAI
SILICIDE-SANDWICHED SOURCE/DRAIN REGION AND METHOD OF FABRICATING SAME (18155887)
Main Inventor
Chung-Hui CHEN
Isolation Layers for Reducing Leakages Between Contacts (17651671)
Main Inventor
Tze-Liang Lee
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18100302)
Main Inventor
Chun-Chieh LU
Dual Damascene Structure in Forming Source/Drain Contacts (17651347)
Main Inventor
Chien-Han Chen
METAL GATE FIN ELECTRODE STRUCTURE AND METHOD (17700998)
Main Inventor
Shih-Hang Chiu
STRUCTURE OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE (18157395)
Main Inventor
Kuo-Cheng CHING
TRANSISTOR SOURCE/DRAIN CONTACTS AND METHODS OF FORMING THE SAME (17651721)
Main Inventor
Pei-Wen Wu
SEMICONDUCTOR DEVICE AND METHOD (17663278)
Main Inventor
Yu-Lien Huang
Semiconductor Device and Method (17744061)
Main Inventor
Wan-Yi Kao
FIN PROFILE MODULATION (17836628)
Main Inventor
Chih-Wei CHIANG
Gate All Around Transistor Device and Fabrication Methods Thereof (18155392)
Main Inventor
Chih-Ching Wang
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES (17569057)
Main Inventor
Ka-Hing FUNG
SEMICONDUCTOR DEVICE (18157906)
Main Inventor
Chi-Chung JEN
DIGITALLY CONTROLLED DELAY LINE CIRCUIT AND METHOD (18155906)
Main Inventor
Chung-Peng HSIEH
FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME (18155932)
Main Inventor
Hidehiro FUJIWARA
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18157461)
Main Inventor
Meng-Sheng Chang
ANTI-FUSE DEVICE AND METHOD (18156625)
Main Inventor
Min-Shin WU
INTEGRATED CIRCUIT INCLUDING EFUSE CELL (18156978)
Main Inventor
Meng-Sheng CHANG
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18157418)
Main Inventor
Meng-Sheng Chang
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18155688)
Main Inventor
Sheng-Chen Wang
TRENCH-TYPE BEOL MEMORY CELL (17672382)
Main Inventor
Tzu-Yu Chen
BIT-LINE RESISTANCE REDUCTION (17690728)
Main Inventor
Yu-Feng Yin
MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD (18156734)
Main Inventor
Meng-Han LIN
