17677929. DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Shih-Ya Lin of Pingtung County (TW)
Chien-Te Tu of Taipei City (TW)
Chung-En Tsai of Hsinchu County (TW)
Chee-Wee Liu of Taipei City (TW)
DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 17677929 titled 'DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF
Simplified Explanation
The patent application describes a device that includes a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The device is built on a substrate and the n-type and p-type source/drain features are positioned on opposite sides of the gate structure. The NFET channel connects the n-type source/drain features, while the PFET channel connects the p-type source/drain features. The NFET channel and PFET channel are vertically spaced apart by the gate structure.
- The device includes a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel.
- The n-type and p-type source/drain features are positioned on opposite sides of the gate structure.
- The NFET channel connects the n-type source/drain features, while the PFET channel connects the p-type source/drain features.
- The NFET channel and PFET channel are vertically spaced apart by the gate structure.
Potential Applications
- Integrated circuits
- Semiconductor devices
- Electronics manufacturing
Problems Solved
- Efficient integration of NFET and PFET channels in a device
- Improved performance and functionality of integrated circuits
Benefits
- Enhanced device performance
- Increased functionality and versatility in electronics manufacturing
- Improved integration of NFET and PFET channels
Original Abstract Submitted
A device comprises a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source/drain features are on opposite first and second sides of the gate structure, respectively. The p-type source/drain features are on opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source/drain features. The PFET channel extends within the gate structure and connects the p-type source/drain features. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.
