18153464. BIT LINE LOGIC CIRCUITS AND METHODS simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
BIT LINE LOGIC CIRCUITS AND METHODS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Jonathan Tsung-Yung Chang of Hsinchu (TW)
Mahmut Sinangil of Hsinchu (TW)
BIT LINE LOGIC CIRCUITS AND METHODS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18153464 titled 'BIT LINE LOGIC CIRCUITS AND METHODS
Simplified Explanation
The patent application describes a circuit that includes a memory cell column coupled to a bit line pair and a write circuit. The write circuit biases the bit lines towards power supply and reference voltage levels in a write operation.
- The circuit includes first and second switching circuits at the second ends of the bit lines.
- Each switching circuit includes first and second logic circuits and first and second switching devices.
- The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the bit line towards the power supply voltage level.
- The second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the bit line towards the reference voltage level.
Potential applications of this technology:
- Memory circuits
- Integrated circuits
- Data storage devices
Problems solved by this technology:
- Efficiently biasing bit lines towards power supply and reference voltage levels in a write operation
- Ensuring proper coupling of bit lines to power supply and reference nodes
Benefits of this technology:
- Improved performance and reliability of memory circuits
- Enhanced data storage and retrieval capabilities
- Efficient use of power supply and reference voltage levels
Original Abstract Submitted
A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.
