18157461. MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Meng-Sheng Chang of Chubei City (TW)
Chia-En Huang of Xinfeng Township (TW)
Yi-Hsun Chiu of Zhubei City (TW)
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18157461 titled 'MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
Simplified Explanation
The abstract describes a memory cell that consists of two transistors, each with a conduction channel made up of nanostructures. One or more of these nanostructures in the first transistor are subjected to stress from a metal structure in the first drain/source region.
- The memory cell includes a first transistor with a conduction channel made of nanostructures.
- The memory cell also includes a second transistor connected in series to the first transistor.
- The second transistor also has a conduction channel made of nanostructures.
- One or more of the nanostructures in the first transistor are subjected to stress from a metal structure in the first drain/source region.
Potential Applications
- Memory cells in electronic devices
- Data storage in computers and mobile devices
Problems Solved
- Enhancing the performance and reliability of memory cells
- Improving the efficiency of data storage and retrieval
Benefits
- Increased speed and efficiency of memory cells
- Improved data storage capacity and reliability
Original Abstract Submitted
A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.
