18155688. THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Sheng-Chen Wang of Hsinchu City (TW)
Sai-Hooi Yeong of Hsinchu County (TW)
Yu-Ming Lin of Hsinchu City (TW)
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18155688 titled 'THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The patent application describes a memory device with a unique structure and configuration. Here are the key points:
- The memory device consists of a first stacking structure and a second stacking structure, separated by a trench.
- First isolation structures are located in the trench, dividing the device into multiple cell regions.
- Each first isolation structure includes a main layer and a liner that separates it from the stacking structures.
- Gate dielectric layers are present in each cell region, covering the sidewalls of the stacking structures and the isolation structures.
- Channel layers are present on the inner surface of the gate dielectric layers.
- Conductive pillars are positioned on the substrate within each cell region, surrounded by the channel layers.
- The conductive pillars are laterally separated from each other within each cell region.
Potential applications of this technology:
- Memory devices with improved performance and efficiency.
- Increased storage capacity in memory devices.
- Suitable for use in various electronic devices, such as smartphones, tablets, and computers.
Problems solved by this technology:
- Provides a more compact and efficient memory device structure.
- Reduces the risk of interference between adjacent memory cells.
- Enhances the overall performance and reliability of the memory device.
Benefits of this technology:
- Higher storage capacity due to the compact structure.
- Improved performance and speed of data retrieval.
- Enhanced reliability and durability of the memory device.
Original Abstract Submitted
A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
