18156123. Reduction of Line Wiggling simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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Reduction of Line Wiggling

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Jiann-Horng Lin of Hsinchu (TW)

Cheng-Li Fan of New Taipei City (TW)

Chih-Hao Chen of Hsinchu (TW)

Reduction of Line Wiggling - A simplified explanation of the abstract

This abstract first appeared for US patent application 18156123 titled 'Reduction of Line Wiggling

Simplified Explanation

The patent application describes a method for reducing wiggling in a line by modifying the height-to-width ratio of a mask layer used in the patterning process. Here are the key points:

  • A silicon patterning layer is formed over a substrate.
  • A mask layer is deposited over the silicon patterning layer.
  • The mask layer is patterned to create openings.
  • The mask layer is thinned and the openings are widened to achieve a smaller height-to-width ratio.
  • The pattern of the mask layer is then used to pattern the silicon patterning layer.
  • The silicon patterning layer is used to pattern a target layer where a metal line will be formed.

Potential applications of this technology:

  • Semiconductor manufacturing
  • Integrated circuit fabrication
  • Nanotechnology research

Problems solved by this technology:

  • Reduces wiggling or distortion in lines during the patterning process.
  • Improves the precision and accuracy of line formation.

Benefits of this technology:

  • Enhanced line quality and integrity
  • Increased manufacturing yield
  • Improved performance and reliability of electronic devices.


Original Abstract Submitted

A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.