18100302. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chun-Chieh Lu of Taipei City (TW)

Carlos H. Diaz of Mountain View CA (US)

Chih-Sheng Chang of Hsinchu (TW)

Cheng-Yi Peng of Taipei City (TW)

Ling-Yen Yeh of Hsinchu City (TW)

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18100302 titled 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The abstract describes a method of manufacturing a negative capacitance structure, which involves forming a dielectric layer over a substrate and then forming a first metallic layer over the dielectric layer. An annealing operation and a cooling operation are performed before forming a second metallic layer. As a result of the cooling operation, the dielectric layer transforms into a ferroelectric dielectric layer with an orthorhombic crystal phase, and the first metallic layer includes an oriented crystalline layer.

  • A dielectric layer is formed over a substrate.
  • A first metallic layer is formed over the dielectric layer.
  • An annealing operation is performed.
  • A cooling operation is performed.
  • A second metallic layer is formed.
  • The dielectric layer transforms into a ferroelectric dielectric layer with an orthorhombic crystal phase.
  • The first metallic layer includes an oriented crystalline layer.

Potential Applications

  • Electronics industry
  • Energy storage devices
  • Capacitors
  • Memory devices

Problems Solved

  • Enhancing the performance of electronic devices
  • Improving energy storage capabilities
  • Increasing the efficiency of capacitors and memory devices

Benefits

  • Improved performance and efficiency of electronic devices
  • Enhanced energy storage capabilities
  • Increased capacitance in capacitors
  • Improved memory retention and retrieval


Original Abstract Submitted

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

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